SRAM_CTRL/RET Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.130s	3.254ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.540s	26.236us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.460s	27.818us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.260s	160.537us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.470s	194.539us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.700s	151.427us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.460s	27.818us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	194.539us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.420s	1.831ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.160s	117.957us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.299m	68.876ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.459m	2.962ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.120s	719.566us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.269m	1.886ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.590s	635.119us	1	1	100.00
V2	executable	sram_ctrl_executable	4.016m	13.018ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.720s	60.059us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.300m	3.816ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.120s	105.175us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.890s	103.932us	1	1	100.00
		sram_ctrl_throughput_w_readback	51.270s	298.671us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.321m	2.050ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.670s	32.417us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.609m	69.829ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.460s	22.452us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.940s	207.281us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.940s	207.281us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.540s	26.236us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	27.818us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	194.539us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	183.026us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.540s	26.236us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	27.818us	1	1	100.00
		sram_ctrl_csr_aliasing	1.470s	194.539us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	183.026us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.080s	433.528us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
		sram_ctrl_tl_intg_err	2.750s	571.908us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.750s	571.908us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.321m	2.050ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.321m	2.050ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.460s	27.818us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.016m	13.018ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.016m	13.018ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.016m	13.018ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.590s	635.119us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.740s	40.270us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.080s	433.528us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.200s	43.004us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.130s	3.254ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.130s	3.254ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.016m	13.018ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.590s	635.119us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.130s	3.254ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	7.096us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.229m	2.348ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.51214307535148934378842983021353158208814230167719707136965681435501347357436
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  43003503 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x46) != exp (0x8)
        UVM_INFO @  43003503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.84405026490273184454854121110622973533480094881794489287160499533347004542355
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  40270371 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  40270371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.15136849400382921538856244448185063749431783593405688722409118579992068756980
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7096163 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7096163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---