SYSRST_CTRL Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.960s 2.110ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.410s 2.492ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.630s 2.152ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.150s 2.301ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.690s 4.029ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.490s 2.095ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 12.270s 39.907ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5.470s 2.681ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 3.040s 2.138ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.490s 2.095ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.470s 2.681ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.702m 158.557ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 24.830s 52.680ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 4.220m 127.652ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.840s 3.390ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.530s 2.512ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.760s 2.237ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 8.940s 3.470ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.630s 2.612ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 6.180s 7.991ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 5.740s 41.006ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 14.420s 6.722ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.930s 2.076ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.170s 2.016ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.900s 2.330ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.900s 2.330ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.690s 4.029ms 1 1 100.00
sysrst_ctrl_csr_rw 2.490s 2.095ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.470s 2.681ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.590s 7.717ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.690s 4.029ms 1 1 100.00
sysrst_ctrl_csr_rw 2.490s 2.095ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.470s 2.681ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.590s 7.717ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.740m 42.014ms 1 1 100.00
sysrst_ctrl_tl_intg_err 30.790s 42.610ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 30.790s 42.610ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.370s 5.356ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00