UART Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.720s	742.839us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.450s	14.462us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.460s	15.076us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.670s	232.875us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.450s	71.685us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.500s	56.778us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.460s	15.076us	1	1	100.00
		uart_csr_aliasing	1.450s	71.685us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	10.230s	40.083ms	1	1	100.00
V2	parity	uart_smoke	1.720s	742.839us	1	1	100.00
		uart_tx_rx	10.230s	40.083ms	1	1	100.00
V2	parity_error	uart_intr	12.980s	46.967ms	1	1	100.00
		uart_rx_parity_err	2.876m	122.123ms	1	1	100.00
V2	watermark	uart_tx_rx	10.230s	40.083ms	1	1	100.00
		uart_intr	12.980s	46.967ms	1	1	100.00
V2	fifo_full	uart_fifo_full	42.990s	32.409ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	17.520s	27.796ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	40.900s	74.548ms	1	1	100.00
V2	rx_frame_err	uart_intr	12.980s	46.967ms	1	1	100.00
V2	rx_break_err	uart_intr	12.980s	46.967ms	1	1	100.00
V2	rx_timeout	uart_intr	12.980s	46.967ms	1	1	100.00
V2	perf	uart_perf	1.275m	9.525ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.780s	5.862ms	1	1	100.00
V2	line_loopback	uart_loopback	3.780s	5.862ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	14.590s	29.130ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.570s	26.172ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.100s	1.238ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.560s	2.143ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.125m	110.318ms	1	1	100.00
V2	stress_all	uart_stress_all	5.119m	618.282ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	13.957us	1	1	100.00
V2	intr_test	uart_intr_test	1.440s	15.446us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.920s	85.509us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.920s	85.509us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.450s	14.462us	1	1	100.00
		uart_csr_rw	1.460s	15.076us	1	1	100.00
		uart_csr_aliasing	1.450s	71.685us	1	1	100.00
		uart_same_csr_outstanding	1.560s	58.799us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.450s	14.462us	1	1	100.00
		uart_csr_rw	1.460s	15.076us	1	1	100.00
		uart_csr_aliasing	1.450s	71.685us	1	1	100.00
		uart_same_csr_outstanding	1.560s	58.799us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.700s	45.790us	1	1	100.00
		uart_tl_intg_err	1.920s	73.887us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.920s	73.887us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.120s	15.841ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00