CHIP Simulation Results

Monday April 28 2025 20:29:11 UTC

GitHub Revision: `841f73f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.004m	2.796ms	1	1	100.00
		chip_sw_example_rom	1.285m	2.794ms	1	1	100.00
		chip_sw_example_manufacturer	1.638m	2.938ms	1	1	100.00
		chip_sw_example_concurrency	2.174m	3.394ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.653m	6.884ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.587m	4.127ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	42.077m	42.213ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.023m	28.074ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	45.390s	1.807ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.023m	28.074ms	1	1	100.00
		chip_csr_rw	2.587m	4.127ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.940s	151.772us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.670m	4.398ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.670m	4.398ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.670m	4.398ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.800m	4.281ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.800m	4.281ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.181m	3.691ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.658m	3.969ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.167m	4.558ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.667m	8.749ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.040m	3.639ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.764m	9.007ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.667m	5.399ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.667m	5.399ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.262m	3.525ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.531m	5.640ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.532m	4.117ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.325m	2.522ms	1	1	100.00
		chip_tap_straps_testunlock0	5.869m	5.877ms	1	1	100.00
		chip_tap_straps_rma	5.110m	6.309ms	1	1	100.00
		chip_tap_straps_prod	1.871m	3.295ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.577m	2.989ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.017m	8.981ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.717m	4.994ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.717m	4.994ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.907m	8.334ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.989m	22.063ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.363m	3.546ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.719m	5.528ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.447m	18.811ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.843m	3.186ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.190m	6.576ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.914m	3.182ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.600m	12.110ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.853m	3.286ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.611m	5.732ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.697m	3.030ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.163m	3.117ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.148m	5.678ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.064m	5.550ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.888m	2.263ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.064m	5.550ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.194m	2.876ms	1	1	100.00
		chip_sw_aes_smoketest	2.853m	3.330ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.722m	3.214ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.974m	2.899ms	1	1	100.00
		chip_sw_csrng_smoketest	2.739m	2.388ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.958m	3.457ms	1	1	100.00
		chip_sw_gpio_smoketest	2.975m	3.216ms	1	1	100.00
		chip_sw_hmac_smoketest	2.593m	2.928ms	1	1	100.00
		chip_sw_kmac_smoketest	2.354m	3.191ms	1	1	100.00
		chip_sw_otbn_smoketest	9.782m	5.950ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.563m	5.275ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.210m	4.950ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.151m	2.722ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.231m	3.419ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.417m	2.500ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.490m	3.040ms	1	1	100.00
		chip_sw_uart_smoketest	2.647m	2.364ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.867m	2.754ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.570m	3.827ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.962h	61.445ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.152m	14.477ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.481m	6.091ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.941m	2.785ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.752m	3.744ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.784h	53.388ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.860h	55.430ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	52.910s	2.260ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	52.910s	2.260ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.023m	28.074ms	1	1	100.00
		chip_same_csr_outstanding	18.540m	15.763ms	1	1	100.00
		chip_csr_hw_reset	3.653m	6.884ms	1	1	100.00
		chip_csr_rw	2.587m	4.127ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.023m	28.074ms	1	1	100.00
		chip_same_csr_outstanding	18.540m	15.763ms	1	1	100.00
		chip_csr_hw_reset	3.653m	6.884ms	1	1	100.00
		chip_csr_rw	2.587m	4.127ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	21.220s	448.934us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.320s	57.700us	1	1	100.00
		xbar_smoke_large_delays	56.040s	8.520ms	1	1	100.00
		xbar_smoke_slow_rsp	53.850s	6.106ms	1	1	100.00
		xbar_random_zero_delays	30.650s	595.067us	1	1	100.00
		xbar_random_large_delays	3.605m	36.016ms	1	1	100.00
		xbar_random_slow_rsp	1.751m	10.558ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	24.650s	1.107ms	1	1	100.00
		xbar_error_and_unmapped_addr	15.900s	188.425us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	17.780s	340.804us	1	1	100.00
		xbar_error_and_unmapped_addr	15.900s	188.425us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	24.030s	1.099ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.391m	55.313ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	26.460s	1.793ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	53.880s	1.107ms	1	1	100.00
		xbar_stress_all_with_error	45.940s	2.417ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.133m	2.415ms	1	1	100.00
		xbar_stress_all_with_reset_error	5.410m	12.731ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.152m	14.477ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.068m	29.774ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.573m	15.164ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.931m	11.004ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.418m	15.931ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.426m	15.534ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.013m	15.404ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.228m	14.600ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.740s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.890s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	26.380s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.220s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.780s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.930s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.700s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.170s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.440s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.550s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.570s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.560s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.340s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.390s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	29.340s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	24.640s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	24.850s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.220s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.750s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.620s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.350s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	29.090s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	28.870s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.170s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.710s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.121m	11.708ms	1	1	100.00
		rom_e2e_asm_init_dev	38.774m	15.265ms	1	1	100.00
		rom_e2e_asm_init_prod	38.839m	15.949ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.904m	15.674ms	1	1	100.00
		rom_e2e_asm_init_rma	35.388m	15.667ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.680m	15.115ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.124m	15.544ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.860m	15.527ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.992m	16.123ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.208m	18.945ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.208m	18.945ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.457m	2.771ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.843m	3.186ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.841m	3.007ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.991m	3.071ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.701m	12.548ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.449m	2.742ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.671m	4.406ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.036m	5.322ms	1	1	100.00
		chip_plic_all_irqs_10	4.533m	4.010ms	1	1	100.00
		chip_plic_all_irqs_20	5.889m	4.071ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.882m	3.151ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.806m	12.294ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.913m	4.369ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.677m	2.801ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.061m	9.759ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.433m	7.531ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.340m	6.936ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.800m	8.038ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.037h	254.772ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.906m	4.348ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.563m	5.275ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.906m	4.348ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.645m	9.446ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.645m	9.446ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.490m	7.715ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.673m	3.826ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.515m	5.580ms	1	1	100.00
		chip_sw_aes_idle	2.991m	3.071ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.667m	3.390ms	1	1	100.00
		chip_sw_kmac_idle	2.270m	2.987ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.708m	5.362ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.757m	5.125ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.623m	4.181ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.415m	5.212ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.948m	11.321ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.471m	4.546ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.060m	4.845ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.933m	3.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.658m	4.283ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.359m	3.484ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.002m	4.986ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.907m	8.334ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.513m	13.321ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.933m	3.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.658m	4.283ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.363m	3.546ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.719m	5.528ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.447m	18.811ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.843m	3.186ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.190m	6.576ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.914m	3.182ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.600m	12.110ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.853m	3.286ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.611m	5.732ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.697m	3.030ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.954m	2.242ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.348m	4.799ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.687m	7.567ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.371m	23.940ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.582m	3.025ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.290m	3.346ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.659m	7.956ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.710m	2.570ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.949m	5.248ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.035m	19.828ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	33.809m	20.269ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.907m	8.334ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.185m	4.814ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.547m	3.486ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.433m	7.531ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.294m	7.570ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.642m	3.052ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.417m	7.380ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.851m	2.620ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.005h	23.592ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.102m	2.947ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.058m	5.554ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.102m	2.947ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.294m	7.570ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.578m	2.915ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.813m	23.812ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.281m	4.844ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.719m	5.528ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.841m	4.434ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.363m	3.546ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	52.461m	43.758ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.813m	23.812ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.361m	3.682ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	52.461m	43.758ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.298m	7.716ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.652m	4.854ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.422m	5.059ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.422m	5.059ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.221m	2.783ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.914m	3.182ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.667m	3.390ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.860m	3.038ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.869m	7.676ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.127m	5.375ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	4.831m	4.274ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	4.474m	4.547ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.264m	4.060ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.600m	12.110ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.387m	7.148ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.701m	12.548ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	28.208m	9.834ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.648m	3.084ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.951m	2.950ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.853m	3.286ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.980m	3.260ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	11.189m	5.857ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.270m	2.987ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.671m	4.406ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.325m	2.522ms	1	1	100.00
		chip_tap_straps_rma	5.110m	6.309ms	1	1	100.00
		chip_tap_straps_prod	1.871m	3.295ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.897m	3.028ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.390m	9.475ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.884m	4.244ms	1	1	100.00
		chip_sw_flash_rma_unlocked	52.461m	43.758ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.888m	2.803ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.241m	6.757ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.685m	5.261ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.859m	7.080ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.415m	9.124ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.050m	7.918ms	1	1	100.00
		chip_prim_tl_access	2.298m	7.716ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.513m	13.321ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.471m	4.546ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.060m	4.845ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.933m	3.310ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.658m	4.283ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.359m	3.484ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.002m	4.986ms	1	1	100.00
		chip_tap_straps_dev	1.325m	2.522ms	1	1	100.00
		chip_tap_straps_rma	5.110m	6.309ms	1	1	100.00
		chip_tap_straps_prod	1.871m	3.295ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.071m	17.185ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.860m	3.393ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.389m	2.963ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.631m	2.903ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.407m	4.048ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.662m	23.634ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.071m	17.185ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	59.500m	46.854ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.091h	48.078ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.040m	8.746ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.584m	47.246ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.662m	23.634ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.171m	2.336ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.067m	1.746ms	1	1	100.00
		rom_volatile_raw_unlock	1.114m	2.260ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.583m	16.825ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.447m	18.811ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.515m	5.580ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.515m	5.580ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.515m	5.580ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.968m	3.046ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.813m	23.812ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.968m	3.046ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.581m	5.072ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.097m	3.071ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.813m	23.812ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.968m	3.046ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.382m	7.219ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.581m	5.072ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.097m	3.071ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.568m	3.625ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.897m	3.028ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.888m	2.803ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.241m	6.757ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.685m	5.261ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.859m	7.080ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.155m	5.178ms	1	1	100.00
		chip_prim_tl_access	2.298m	7.716ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.298m	7.716ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.633m	8.614ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.170m	8.254ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.616m	26.443ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.902m	7.299ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.987m	7.646ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	8.038m	7.176ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.802m	19.868ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.449m	17.731ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.645m	9.446ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.571m	12.463ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.550m	4.516ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.170m	8.254ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.214m	4.856ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	35.160m	35.396ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.931m	5.660ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.684m	3.962ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	13.711m	20.132ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.619m	7.437ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.307m	9.634ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.681m	23.373ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.662m	3.354ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.415m	9.124ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.415m	9.124ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.307m	9.634ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	13.711m	20.132ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	4.550m	4.516ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.563m	5.275ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.351m	3.620ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.122m	4.991ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.692m	4.111ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.806m	12.294ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.996m	2.527ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.340m	6.936ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.629m	5.174ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.296m	4.798ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.645m	3.123ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.097m	3.071ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.122m	4.991ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.122m	4.991ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.428m	5.011ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.524m	13.121ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.351m	3.620ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.259m	4.270ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.211m	6.754ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	5.110m	6.309ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.071m	17.185ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.036m	5.322ms	1	1	100.00
		chip_plic_all_irqs_10	4.533m	4.010ms	1	1	100.00
		chip_plic_all_irqs_20	5.889m	4.071ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.605m	3.436ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.460m	3.054ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.152m	14.477ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.925m	7.710ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.097m	3.183ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.959m	3.068ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.205m	3.396ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.581m	5.072ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.611m	5.732ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.904m	8.442ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.792m	7.066ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.050m	7.918ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.717m	4.994ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.619m	7.437ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.182m	24.674ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.843m	2.778ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.836m	3.455ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.052m	4.651ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.182m	24.674ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.182m	24.674ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.889m	10.678ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.889m	10.678ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.379m	6.354ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.208m	18.945ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.946m	2.867ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.885m	3.482ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.104m	3.977ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.995m	4.054ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.834m	8.441ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.327h	31.420ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.081m	11.908ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.880m	3.002ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.468m	2.836ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.465m	2.670ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.359h	71.536ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.488m	5.357ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.320m	10.786ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.120m	12.486ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.431m	11.059ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.130m	4.343ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.090m	4.690ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.583m	4.366ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.446s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.035m	4.959ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.862m	3.078ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.282m	4.851ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	26.048m	10.744ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.672m	2.768ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.238m	5.917ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.425m	2.088ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.252m	5.986ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.206m	5.399ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.936m	4.372ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.307m	9.634ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.320m	10.786ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.120m	12.486ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.431m	11.059ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.107m	6.163ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.315m	5.118ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.438h	38.739ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.438h	38.739ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.819m	2.986ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.800m	4.281ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.752m	19.502ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.282m	3.178ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.202m	5.184ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.659m	3.070ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.458m	2.660ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.913m	3.264ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	16.604s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.685m	3.321ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.31869709462712891744203675571362886179075578701652719449667603633282056119019
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.15221179596995281633865878883822437949476948312670783232291420362211504625333
    Line 802, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.90155928414136737901049459157249972681088201590712842256570289100051310215859
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.104199855432953183045202914317355608343891375789807439563296089908161581276198
    Line 753, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.114426196170029681583478013783498423257522453925993923940468702099393218471472
    Line 794, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.76440974803413377149763866339854789746433453721436653183422050947123047259622
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.19932514951094242427788782350956124223371444490680294081912846966399387420211
    Line 737, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.96413750568333355536929251218577147824012284998455186175748388662965369746847
    Line 653, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.87367578114000815376748531947565400744633890107797523874166983056534582343494
    Line 736, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.51459646723521665092132517453675353453022539334815270227170224977606197846714
    Line 724, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.79959673827724836875109045906942071232076798036894966254082824461889662657204
    Line 805, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.108226440568673091511567425078509979402815788448040037283939445031080374014775
    Line 750, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.78394469078328183537564922299367564663743240302219356600588998248030595048680
    Line 759, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.16737331982636882073885380611177020624953514508308782401076191195419036158146
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.487s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1379410223774444259354784003355405382351738408740118913880171320920895204989
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 7.569s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.72774244888997092158447585985356298977037551880579518946741758148161933093496
    Line 967, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3997911058714103280645918482700873770072104617809722879876495925618033948011
    Line 751, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.17125273685506609166960454451004771232552113882490924051835388361673971169072
    Line 1023, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.15230865375138501833531315918619895724301751394253466126900106277724128607451
    Line 683, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.15072727619470195045779263986866136571058327571433171473679300725365692757654
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3182.568552 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3182.568552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94613) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.36774734246716550215043693048338970583393508654230362387082360954727295467192
Line 449, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4990.852420 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94613) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4990.852420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.21463891409200058302326304790997128631543478304234531645016455697349122622245
    Line 504, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 20131.518126 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 20131.518126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.114332004743282347049212710094972175037133438406665909187144674186642601019953
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10677.585448 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10677.585448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.36711987087345769225163299632166485407862741141729099937055888504020575443660
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2742.127140 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2742.127140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.13673002888784756579171141265309984769857459161151644087851070787756864491084
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2801.330200 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2801.330200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.100602510016028608231287912633129102081528053269722496388741443088877780398069
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3051.684331 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3051.684331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33119) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.40342723414994851187414787644234525064875162127029267192759269036849141171079
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2259.535720 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33119) { a_addr: 'h10664  a_data: 'h4acac8ba  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h1a263  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2259.535720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.62762234570057863108183619858644928740565473965656067610839432203224176521793
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3264.337604 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3264.337604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.61325372861960958202434495570473259727591136961305298937236630316542692987675
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2784.962500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2784.962500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.106353164240179701070071996217786891493336003712158090891764963133702139406656
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3743.534500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3743.534500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.114269746589601810084660378045098767845454247362245296184071418597646477126274
    Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22062.759323 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22062.759323 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.113977557499167879710641960962587672212197856080012251842330234845943674169264
    Line 706, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.92067529461470069827579553851897991318776611265693147258751705110696748122018
    Line 860, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32637) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.85451282624934560967312075692397192468882122770237647387888264173676535322326
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1806.929620 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32637) { a_addr: 'h10628  a_data: 'hc60df922  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h192c7  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1806.929620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---