ADC_CTRL Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.900s	5.937ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.860s	1.045ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.290s	362.394us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	53.510s	38.664ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.520s	1.056ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	403.391us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.290s	362.394us	1	1	100.00
		adc_ctrl_csr_aliasing	4.520s	1.056ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.355m	334.324ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.828m	321.947ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.880m	493.086ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	5.045m	162.228ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.396m	174.080ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	4.505m	590.498ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	9.330m	324.094ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	50.790s	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.540s	3.675ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	55.300s	32.977ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	50.010s	69.630ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.542m	356.011ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.520s	483.607us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.290s	504.821us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.390s	401.871us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.390s	401.871us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.860s	1.045ms	1	1	100.00
		adc_ctrl_csr_rw	2.290s	362.394us	1	1	100.00
		adc_ctrl_csr_aliasing	4.520s	1.056ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.130s	3.999ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.860s	1.045ms	1	1	100.00
		adc_ctrl_csr_rw	2.290s	362.394us	1	1	100.00
		adc_ctrl_csr_aliasing	4.520s	1.056ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.130s	3.999ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	15.550s	7.947ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.730s	4.406ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.730s	4.406ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.170s	5.880ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.4052691889757340110093010683443124823850382788884221092577793976227699849093
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---