EDN Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.840s 20.432us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.690s 55.483us 1 1 100.00
V1 csr_rw edn_csr_rw 1.840s 45.934us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.380s 117.557us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.910s 84.499us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 29.201us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.840s 45.934us 1 1 100.00
edn_csr_aliasing 1.910s 84.499us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.900s 61.352us 1 1 100.00
V2 csrng_commands edn_genbits 1.900s 61.352us 1 1 100.00
V2 genbits edn_genbits 1.900s 61.352us 1 1 100.00
V2 interrupts edn_intr 1.700s 34.686us 1 1 100.00
V2 alerts edn_alert 2.130s 50.804us 1 1 100.00
V2 errs edn_err 1.850s 57.499us 1 1 100.00
V2 disable edn_disable 1.720s 16.054us 1 1 100.00
edn_disable_auto_req_mode 1.960s 29.131us 1 1 100.00
V2 stress_all edn_stress_all 3.420s 319.386us 1 1 100.00
V2 intr_test edn_intr_test 1.720s 29.085us 1 1 100.00
V2 alert_test edn_alert_test 1.930s 47.245us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.000s 54.582us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.000s 54.582us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.690s 55.483us 1 1 100.00
edn_csr_rw 1.840s 45.934us 1 1 100.00
edn_csr_aliasing 1.910s 84.499us 1 1 100.00
edn_same_csr_outstanding 1.760s 172.686us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.690s 55.483us 1 1 100.00
edn_csr_rw 1.840s 45.934us 1 1 100.00
edn_csr_aliasing 1.910s 84.499us 1 1 100.00
edn_same_csr_outstanding 1.760s 172.686us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.520s 893.944us 1 1 100.00
edn_tl_intg_err 3.310s 158.147us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.730s 31.332us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.130s 50.804us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.520s 893.944us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.520s 893.944us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.520s 893.944us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.520s 893.944us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.130s 50.804us 1 1 100.00
edn_sec_cm 6.520s 893.944us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.130s 50.804us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.310s 158.147us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets