HMAC Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.620s 104.854us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.700s 63.173us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.930s 116.416us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.090s 479.769us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.070s 3.412ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.540s 41.113us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.930s 116.416us 1 1 100.00
hmac_csr_aliasing 7.070s 3.412ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 24.930s 1.276ms 1 1 100.00
V2 back_pressure hmac_back_pressure 56.960s 17.180ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.911m 11.116ms 1 1 100.00
hmac_test_sha384_vectors 5.906m 11.149ms 1 1 100.00
hmac_test_sha512_vectors 22.640s 214.648us 1 1 100.00
hmac_test_hmac256_vectors 6.770s 792.144us 1 1 100.00
hmac_test_hmac384_vectors 9.110s 225.155us 1 1 100.00
hmac_test_hmac512_vectors 15.230s 325.108us 1 1 100.00
V2 burst_wr hmac_burst_wr 21.560s 2.029ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 51.860s 873.533us 1 1 100.00
V2 error hmac_error 7.240s 130.785us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.273m 8.974ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.620s 104.854us 1 1 100.00
hmac_long_msg 24.930s 1.276ms 1 1 100.00
hmac_back_pressure 56.960s 17.180ms 1 1 100.00
hmac_datapath_stress 51.860s 873.533us 1 1 100.00
hmac_burst_wr 21.560s 2.029ms 1 1 100.00
hmac_stress_all 1.940m 13.314ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.620s 104.854us 1 1 100.00
hmac_long_msg 24.930s 1.276ms 1 1 100.00
hmac_back_pressure 56.960s 17.180ms 1 1 100.00
hmac_datapath_stress 51.860s 873.533us 1 1 100.00
hmac_wipe_secret 1.273m 8.974ms 1 1 100.00
hmac_test_sha256_vectors 2.911m 11.116ms 1 1 100.00
hmac_test_sha384_vectors 5.906m 11.149ms 1 1 100.00
hmac_test_sha512_vectors 22.640s 214.648us 1 1 100.00
hmac_test_hmac256_vectors 6.770s 792.144us 1 1 100.00
hmac_test_hmac384_vectors 9.110s 225.155us 1 1 100.00
hmac_test_hmac512_vectors 15.230s 325.108us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.620s 104.854us 1 1 100.00
hmac_long_msg 24.930s 1.276ms 1 1 100.00
hmac_back_pressure 56.960s 17.180ms 1 1 100.00
hmac_datapath_stress 51.860s 873.533us 1 1 100.00
hmac_burst_wr 21.560s 2.029ms 1 1 100.00
hmac_error 7.240s 130.785us 1 1 100.00
hmac_wipe_secret 1.273m 8.974ms 1 1 100.00
hmac_test_sha256_vectors 2.911m 11.116ms 1 1 100.00
hmac_test_sha384_vectors 5.906m 11.149ms 1 1 100.00
hmac_test_sha512_vectors 22.640s 214.648us 1 1 100.00
hmac_test_hmac256_vectors 6.770s 792.144us 1 1 100.00
hmac_test_hmac384_vectors 9.110s 225.155us 1 1 100.00
hmac_test_hmac512_vectors 15.230s 325.108us 1 1 100.00
hmac_stress_all 1.940m 13.314ms 1 1 100.00
V2 stress_all hmac_stress_all 1.940m 13.314ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 39.661us 1 1 100.00
V2 intr_test hmac_intr_test 1.610s 14.521us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.870s 174.935us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.870s 174.935us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.700s 63.173us 1 1 100.00
hmac_csr_rw 1.930s 116.416us 1 1 100.00
hmac_csr_aliasing 7.070s 3.412ms 1 1 100.00
hmac_same_csr_outstanding 2.360s 36.555us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.700s 63.173us 1 1 100.00
hmac_csr_rw 1.930s 116.416us 1 1 100.00
hmac_csr_aliasing 7.070s 3.412ms 1 1 100.00
hmac_same_csr_outstanding 2.360s 36.555us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.110s 253.639us 1 1 100.00
hmac_tl_intg_err 4.610s 1.647ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.610s 1.647ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.620s 104.854us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.250s 252.834us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 53.080s 36.556ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.620s 198.442us 1 1 100.00
TOTAL 28 28 100.00