I2C Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: `e07399c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.430s	2.901ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.860s	1.407ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.680s	102.752us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.690s	23.039us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.200s	441.719us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.960s	54.932us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.910s	48.088us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.690s	23.039us	1	1	100.00
		i2c_csr_aliasing	1.960s	54.932us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	6.430s	217.695us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all			0	1	0.00
V2	host_maxperf	i2c_host_perf	1.030m	7.594ms	1	1	100.00
V2	host_override	i2c_host_override	1.770s	130.370us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.877m	5.337ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.048m	9.045ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.830s	123.803us	1	1	100.00
		i2c_host_fifo_fmt_empty	12.400s	347.685us	1	1	100.00
		i2c_host_fifo_reset_rx	3.390s	267.915us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.694m	2.510ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.250s	1.784ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.380s	633.149us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.950s	14.840ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	26.780s	26.743ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.810s	816.389us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	22.770s	1.655ms	1	1	100.00
		i2c_target_intr_smoke	6.080s	1.348ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.780s	408.811us	1	1	100.00
		i2c_target_fifo_reset_tx	2.670s	317.368us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	22.200s	33.382ms	1	1	100.00
		i2c_target_stress_rd	22.770s	1.655ms	1	1	100.00
		i2c_target_intr_stress_wr	11.060s	7.293ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.640s	5.030ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.860s	1.379ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.710s	4.176ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.120s	488.405us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.520s	588.340us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.710s	173.280us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.030m	7.594ms	1	1	100.00
		i2c_host_perf_precise	7.000s	2.654ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.250s	1.784ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.390s	329.035us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.720s	2.157ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.810s	544.699us	1	1	100.00
		i2c_target_nack_txstretch	2.170s	146.992us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	18.800s	666.232us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.300s	422.677us	1	1	100.00
V2	alert_test	i2c_alert_test	1.570s	25.882us	1	1	100.00
V2	intr_test	i2c_intr_test	1.730s	26.000us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.670s	347.003us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.670s	347.003us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.680s	102.752us	1	1	100.00
		i2c_csr_rw	1.690s	23.039us	1	1	100.00
		i2c_csr_aliasing	1.960s	54.932us	1	1	100.00
		i2c_same_csr_outstanding	1.910s	66.617us	0	1	0.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.680s	102.752us	1	1	100.00
		i2c_csr_rw	1.690s	23.039us	1	1	100.00
		i2c_csr_aliasing	1.960s	54.932us	1	1	100.00
		i2c_same_csr_outstanding	1.910s	66.617us	0	1	0.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	3.250s	146.501us	1	1	100.00
		i2c_sec_cm	2.040s	246.332us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.250s	146.501us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.340s	1.049ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.140s	116.617us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	25.020s	2.026ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.75856190740469056445523041803551708398114570289483167652772802059314816103401
    Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1049336351 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1049336351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.69307697162710896423571883691662606851397443868701639852240639260143735457442
    Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2026209866 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2026209866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 0.i2c_host_stress_all.33379297222754905872157332688587154643498448915949640921213616745930401251146
    Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.11305454670782153642540722020100583565071016955400866907725649424630901988673
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 116617385 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 116617385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.60877310340934984498434749731004091604649577360130134185638743728729818967497
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 633149358 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @36491

UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 0.i2c_same_csr_outstanding.26245430511033249697231920345390695345522407722049430803541322834181953472108
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  66616650 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  66616650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```