KEYMGR Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.780s	347.821us	1	1	100.00
V1	random	keymgr_random	4.050s	102.831us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.580s	19.796us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.730s	21.495us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.060s	138.930us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.430s	359.046us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.190s	32.807us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.730s	21.495us	1	1	100.00
		keymgr_csr_aliasing	8.430s	359.046us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	6.990s	317.714us	1	1	100.00
V2	sideload	keymgr_sideload	3.030s	418.458us	1	1	100.00
		keymgr_sideload_kmac	2.940s	134.520us	1	1	100.00
		keymgr_sideload_aes	6.880s	344.693us	1	1	100.00
		keymgr_sideload_otbn	2.820s	173.601us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.340s	63.066us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.080s	93.066us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.540s	752.163us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	27.790s	1.798ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.090s	142.461us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.130s	2.685ms	1	1	100.00
V2	stress_all	keymgr_stress_all	19.680s	735.609us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.660s	22.520us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.590s	17.370us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.120s	51.574us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.120s	51.574us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.580s	19.796us	1	1	100.00
		keymgr_csr_rw	1.730s	21.495us	1	1	100.00
		keymgr_csr_aliasing	8.430s	359.046us	0	1	0.00
		keymgr_same_csr_outstanding	1.720s	92.399us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.580s	19.796us	1	1	100.00
		keymgr_csr_rw	1.730s	21.495us	1	1	100.00
		keymgr_csr_aliasing	8.430s	359.046us	0	1	0.00
		keymgr_same_csr_outstanding	1.720s	92.399us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
		keymgr_tl_intg_err	2.040s	17.780us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.110s	293.181us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.110s	293.181us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.110s	293.181us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.110s	293.181us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.260s	1.906ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.040s	17.780us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.110s	293.181us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	6.990s	317.714us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.050s	102.831us	1	1	100.00
		keymgr_csr_rw	1.730s	21.495us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.050s	102.831us	1	1	100.00
		keymgr_csr_rw	1.730s	21.495us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.050s	102.831us	1	1	100.00
		keymgr_csr_rw	1.730s	21.495us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.080s	93.066us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.090s	142.461us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.090s	142.461us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.050s	102.831us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.860s	349.447us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.660s	146.714us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.080s	93.066us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.660s	146.714us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.660s	146.714us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.660s	146.714us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.140s	2.139ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.660s	146.714us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.070s	293.081us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.56515183341395728193988946355374656040507490541448377041243031146841365031800
      Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @  17779665 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @  17779665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.17692714939986862529519357674766383216395049355655169512301375038152844072946
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 359045741 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 359045741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.48471204790580956694028882620824007399957640630801823286024618354574262094864
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
        UVM_ERROR @  92398538 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
        UVM_INFO @  92398538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.3880092713299714626255224685333693974820189701821753684010791459562020687719
      Line 107, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 293081437 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 293081437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---