KMAC/MASKED Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	12.700s	2.894ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	52.987us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	82.132us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.820s	1.936ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.470s	780.194us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.490s	73.371us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	82.132us	1	1	100.00
		kmac_csr_aliasing	7.470s	780.194us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	11.986us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.780s	22.155us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.745m	8.185ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.843m	98.105ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.429m	1.496s	1	1	100.00
		kmac_test_vectors_sha3_256	28.284m	57.887ms	1	1	100.00
		kmac_test_vectors_sha3_384	25.879m	145.334ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.070s	1.285ms	1	1	100.00
		kmac_test_vectors_shake_128	2.327m	35.922ms	1	1	100.00
		kmac_test_vectors_shake_256	1.769m	7.206ms	1	1	100.00
		kmac_test_vectors_kmac	3.730s	649.489us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.000s	50.202us	1	1	100.00
V2	sideload	kmac_sideload	4.752m	80.807ms	1	1	100.00
V2	app	kmac_app	40.400s	38.887ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.846m	6.937ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.718m	21.531ms	1	1	100.00
V2	error	kmac_error	40.370s	1.407ms	1	1	100.00
V2	key_error	kmac_key_error	11.290s	1.228ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.330s	125.375us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	30.950s	5.520ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.360s	114.309us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	40.980s	6.770ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	26.850s	3.655ms	1	1	100.00
V2	stress_all	kmac_stress_all	33.340s	1.579ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.600s	33.985us	1	1	100.00
V2	alert_test	kmac_alert_test	1.700s	51.686us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.410s	71.899us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.410s	71.899us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	52.987us	1	1	100.00
		kmac_csr_rw	1.910s	82.132us	1	1	100.00
		kmac_csr_aliasing	7.470s	780.194us	1	1	100.00
		kmac_same_csr_outstanding	2.600s	146.638us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	52.987us	1	1	100.00
		kmac_csr_rw	1.910s	82.132us	1	1	100.00
		kmac_csr_aliasing	7.470s	780.194us	1	1	100.00
		kmac_same_csr_outstanding	2.600s	146.638us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	597.233us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	597.233us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	597.233us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	597.233us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.020s	63.752us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	40.970s	8.127ms	1	1	100.00
		kmac_tl_intg_err	1.610s	9.156us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.610s	9.156us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	26.850s	3.655ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	12.700s	2.894ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.752m	80.807ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	597.233us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	40.970s	8.127ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	40.970s	8.127ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	40.970s	8.127ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	12.700s	2.894ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	26.850s	3.655ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	40.970s	8.127ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.283m	11.259ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	12.700s	2.894ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.364m	17.342ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.29722869265216098854516435309645569714497842954804599380844745243534276689043
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  63751867 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  63751867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.92775989739707425762097194486039016995515028477220501405085462276460584050320
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @   9155547 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @   9155547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---