KMAC/UNMASKED Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	22.550s	5.847ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.620s	108.304us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.700s	23.046us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.000s	563.638us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.060s	141.688us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.990s	210.388us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.700s	23.046us	1	1	100.00
		kmac_csr_aliasing	4.060s	141.688us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.990s	38.889us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.930s	182.195us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3.170m	40.796ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.489m	2.927ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.190s	3.607ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.130s	8.570ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.676m	13.109ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.889m	193.085ms	1	1	100.00
		kmac_test_vectors_shake_128	2.441m	38.086ms	1	1	100.00
		kmac_test_vectors_shake_256	26.732m	176.630ms	1	1	100.00
		kmac_test_vectors_kmac	2.660s	29.816us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.460s	276.725us	1	1	100.00
V2	sideload	kmac_sideload	3.218m	4.248ms	1	1	100.00
V2	app	kmac_app	3.155m	25.596ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	22.360s	1.554ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	53.840s	40.074ms	1	1	100.00
V2	error	kmac_error	3.424m	4.049ms	1	1	100.00
V2	key_error	kmac_key_error	9.230s	6.020ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.370s	113.518us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.960s	6.654ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.350s	1.655ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	41.630s	54.551ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.010s	424.416us	1	1	100.00
V2	stress_all	kmac_stress_all	9.951m	98.331ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.690s	25.976us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	37.386us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.110s	261.026us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.110s	261.026us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.620s	108.304us	1	1	100.00
		kmac_csr_rw	1.700s	23.046us	1	1	100.00
		kmac_csr_aliasing	4.060s	141.688us	1	1	100.00
		kmac_same_csr_outstanding	2.780s	56.162us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.620s	108.304us	1	1	100.00
		kmac_csr_rw	1.700s	23.046us	1	1	100.00
		kmac_csr_aliasing	4.060s	141.688us	1	1	100.00
		kmac_same_csr_outstanding	2.780s	56.162us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.800s	91.072us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.800s	91.072us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.800s	91.072us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.800s	91.072us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	103.112us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	25.560s	2.773ms	1	1	100.00
		kmac_tl_intg_err	3.970s	1.083ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.970s	1.083ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.010s	424.416us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	22.550s	5.847ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.218m	4.248ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.800s	91.072us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.560s	2.773ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.560s	2.773ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.560s	2.773ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	22.550s	5.847ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.010s	424.416us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.560s	2.773ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.369m	2.996ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	22.550s	5.847ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.610s	1.486ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.48613833024047150642931149578153875200613719845911348782041831194048526961843
      Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1485910579 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1485910579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---