OTBN Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	128.987us	1	1	100.00
V1	single_binary	otbn_single	10.000s	21.653us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	16.166us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	20.911us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	75.290us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	18.748us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	48.309us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	20.911us	1	1	100.00
		otbn_csr_aliasing	7.000s	18.748us	1	1	100.00
V1	mem_walk	otbn_mem_walk	29.000s	942.998us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	243.147us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	22.000s	66.469us	1	1	100.00
V2	multi_error	otbn_multi_err	50.000s	147.571us	1	1	100.00
V2	back_to_back	otbn_multi	18.000s	396.110us	1	1	100.00
V2	stress_all	otbn_stress_all	47.000s	587.842us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	69.626us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	13.861us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	15.000s	42.161us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	45.741us	1	1	100.00
V2	intr_test	otbn_intr_test	18.000s	29.925us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	50.000s	19.704us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	50.000s	19.704us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	16.166us	1	1	100.00
		otbn_csr_rw	7.000s	20.911us	1	1	100.00
		otbn_csr_aliasing	7.000s	18.748us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	98.393us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	16.166us	1	1	100.00
		otbn_csr_rw	7.000s	20.911us	1	1	100.00
		otbn_csr_aliasing	7.000s	18.748us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	98.393us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	15.533us	1	1	100.00
		otbn_dmem_err	8.000s	13.855us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	220.771us	1	1	100.00
		otbn_controller_ispr_rdata_err	14.000s	56.818us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	102.339us	1	1	100.00
		otbn_urnd_err	12.000s	22.533us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	65.105us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	27.331us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	26.627us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	15.015us	0	1	0.00
		otbn_tl_intg_err	36.000s	99.762us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.167m	302.314us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	128.987us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	13.855us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	15.533us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	36.000s	99.762us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	69.626us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	15.533us	1	1	100.00
		otbn_dmem_err	8.000s	13.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	13.861us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	65.105us	1	1	100.00
		otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	15.533us	1	1	100.00
		otbn_dmem_err	8.000s	13.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	13.861us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	65.105us	1	1	100.00
		otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	69.626us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	15.533us	1	1	100.00
		otbn_dmem_err	8.000s	13.855us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	13.861us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	65.105us	1	1	100.00
		otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	42.972us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	93.514us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	26.000s	790.266us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	26.000s	790.266us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	40.977us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	107.601us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	31.642us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	31.642us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	29.431us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	18.000s	396.110us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	38.893us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	21.653us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	15.015us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.767m	3.421ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.29540412508624811233250197346703394475662874784631204903095297159316738365134
      Line 449, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3420855238 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3420855238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.115253726203834820031057223019945619693574424818000418596015125342751461107513
      Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29431481 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  29431481 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  29431481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.52965500534407595503894884795793143912783485321246235213482773543081059391582
      Line 91, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 15014762 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 15014762 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  15014762 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  15014762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---