RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.000s 1.979ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.270s 769.990us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.740s 386.775us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 20.980s 35.231ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.060s 1.930ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 6.770s 9.583ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 11.660s 5.253ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 32.520s 16.392ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 25.450s 13.426ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.740s 420.813us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.990s 645.354us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.700s 209.357us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.560s 115.936us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.870s 473.280us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.460s 2.367ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.540s 86.058us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.680s 185.965us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.740s 420.813us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.790s 138.660us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.280s 830.792us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.700s 209.357us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.760s 57.352us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.440s 164.638us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.590s 191.686us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 50.700s 7.317ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.610s 2.365ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.580s 44.846us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.610s 2.365ms 1 1 100.00
rv_dm_csr_rw 2.590s 191.686us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.750s 90.322us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.630s 133.774us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.000s 1.979ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.190s 203.647us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.820s 573.254us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.810s 138.299us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.990s 683.286us 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.660s 912.868us 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.930s 126.386us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.780s 1.911ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.980s 2.522ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.710s 543.868us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.260s 1.281ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.010s 577.265us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.630s 188.608us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 16.150s 16.233ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 3.660s 333.870us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.610s 82.441us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.560s 3.091ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.590s 35.517us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 2.250s 21.231us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 2.250s 21.231us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.610s 2.365ms 1 1 100.00
rv_dm_csr_hw_reset 2.440s 164.638us 1 1 100.00
rv_dm_csr_rw 2.590s 191.686us 1 1 100.00
rv_dm_same_csr_outstanding 6.360s 828.748us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.610s 2.365ms 1 1 100.00
rv_dm_csr_hw_reset 2.440s 164.638us 1 1 100.00
rv_dm_csr_rw 2.590s 191.686us 1 1 100.00
rv_dm_same_csr_outstanding 6.360s 828.748us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.160s 995.858us 1 1 100.00
rv_dm_tl_intg_err 6.650s 1.118ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 6.650s 1.118ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.260s 1.281ms 1 1 100.00
rv_dm_debug_disabled 1.800s 99.185us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.260s 1.281ms 1 1 100.00
rv_dm_debug_disabled 1.800s 99.185us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.000s 1.979ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.010s 86.793us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.840s 320.568us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.840s 320.568us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.010s 86.793us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.650s 17.626us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.640s 11.897us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets