RV_TIMER Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.600s	12.652us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.420s	64.570us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.340s	105.408us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.110s	174.950us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.700s	23.611us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.590s	30.610us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.340s	105.408us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	23.611us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.480s	92.792us	1	1	100.00
V2	disabled	rv_timer_disabled	2.231m	227.126ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.185m	104.229ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.185m	104.229ms	1	1	100.00
V2	stress	rv_timer_stress_all	10.690s	12.392ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.780s	17.130us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.410s	226.354us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.410s	226.354us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.420s	64.570us	1	1	100.00
		rv_timer_csr_rw	1.340s	105.408us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	23.611us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	13.381us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.420s	64.570us	1	1	100.00
		rv_timer_csr_rw	1.340s	105.408us	1	1	100.00
		rv_timer_csr_aliasing	1.700s	23.611us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	13.381us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.950s	539.993us	1	1	100.00
		rv_timer_tl_intg_err	2.100s	250.858us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.100s	250.858us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	50.230s	24.962ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00