SPI_DEVICE/1R1W Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	48.660s	4.974ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.780s	43.242us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.730s	183.742us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.520s	376.867us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.760s	9.423ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.600s	255.623us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.730s	183.742us	1	1	100.00
		spi_device_csr_aliasing	14.760s	9.423ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.400s	16.490us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.320s	22.705us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.720s	50.813us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	3.713us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.550s	3.662us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.900s	1.536ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.900s	1.536ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.170s	7.855ms	1	1	100.00
		spi_device_tpm_sts_read	1.580s	23.652us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.930s	9.590ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.660s	795.116us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.990s	860.753us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.990s	860.753us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.180s	135.487us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.180s	135.487us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.180s	135.487us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.180s	135.487us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.180s	135.487us	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.970s	1.020ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	13.570s	3.622ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.570s	3.622ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.570s	3.622ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.840s	50.670us	1	1	100.00
		spi_device_read_buffer_direct	5.360s	9.847ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.570s	3.622ms	1	1	100.00
		spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	36.030s	20.415ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.540s	268.803us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.540s	268.803us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	48.660s	4.974ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.206m	114.468ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.747m	98.786ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.700s	14.138us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.500s	15.319us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.670s	183.041us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.670s	183.041us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.780s	43.242us	1	1	100.00
		spi_device_csr_rw	2.730s	183.742us	1	1	100.00
		spi_device_csr_aliasing	14.760s	9.423ms	1	1	100.00
		spi_device_same_csr_outstanding	3.430s	77.125us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.780s	43.242us	1	1	100.00
		spi_device_csr_rw	2.730s	183.742us	1	1	100.00
		spi_device_csr_aliasing	14.760s	9.423ms	1	1	100.00
		spi_device_same_csr_outstanding	3.430s	77.125us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.910s	481.019us	1	1	100.00
		spi_device_tl_intg_err	12.380s	4.648ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.380s	4.648ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.032m	202.987ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.110995310944894221328562562436144196658227054767655296435198105429569356621488
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2488757 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[86])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2488757 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2488757 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[982])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.14545022916780297570627689284707612364752789605598771914122363281777264802679
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3142123 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3142123 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   3221123 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b9e63 [110111001111001100011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3221123 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x1b9e63 [110111001111001100011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])