SPI_DEVICE/2P Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.723m	25.580ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.880s	47.205us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.810s	20.329us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.550s	2.530ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.840s	116.017us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.420s	188.922us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.810s	20.329us	1	1	100.00
		spi_device_csr_aliasing	5.840s	116.017us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	11.125us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	47.112us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	62.929us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.750s	61.597us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	3.366us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.840s	59.038us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.840s	59.038us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.760s	99.845us	1	1	100.00
		spi_device_tpm_sts_read	1.630s	48.330us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.080s	17.486ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.110s	11.552ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.650s	282.178us	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.650s	282.178us	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.320s	1.718ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.320s	1.718ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.320s	1.718ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.320s	1.718ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.320s	1.718ms	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.800s	5.136ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.150s	234.991us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.150s	234.991us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.150s	234.991us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.820s	530.898us	1	1	100.00
		spi_device_read_buffer_direct	6.680s	3.759ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.150s	234.991us	1	1	100.00
		spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.010s	10.356us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.020s	475.653us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.020s	475.653us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.723m	25.580ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.320s	1.829ms	1	1	100.00
V2	stress_all	spi_device_stress_all	6.918m	142.447ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.650s	43.084us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.580s	48.517us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.380s	260.704us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.380s	260.704us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.880s	47.205us	1	1	100.00
		spi_device_csr_rw	1.810s	20.329us	1	1	100.00
		spi_device_csr_aliasing	5.840s	116.017us	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	66.434us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.880s	47.205us	1	1	100.00
		spi_device_csr_rw	1.810s	20.329us	1	1	100.00
		spi_device_csr_aliasing	5.840s	116.017us	1	1	100.00
		spi_device_same_csr_outstanding	2.350s	66.434us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.080s	195.409us	1	1	100.00
		spi_device_tl_intg_err	8.640s	193.307us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.640s	193.307us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	23.750s	5.569ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.56620531641690818143094173253513401462738905826713529437623007483991477133181
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2747487 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2747487 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   2755487 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xe2a195 [111000101010000110010101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   2755487 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)