SPI_HOST Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.750m	10.459ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	80.189us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	48.734us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	956.420us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	32.721us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	19.076us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	48.734us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.721us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	33.710us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	17.922us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	30.622us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	192.362us	1	1	100.00
		spi_host_error_cmd	4.000s	54.126us	1	1	100.00
		spi_host_event	9.000s	766.236us	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	742.358us	1	1	100.00
V2	speed	spi_host_speed	7.000s	742.358us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	742.358us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	168.016us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	257.491us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	742.358us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	742.358us	1	1	100.00
V2	duplex	spi_host_smoke	2.750m	10.459ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	2.750m	10.459ms	1	1	100.00
V2	stress_all	spi_host_stress_all	31.000s	6.106ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	550.303us	1	1	100.00
V2	stall	spi_host_status_stall	40.000s	13.056ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	138.349us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	192.362us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.161us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	28.245us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	491.037us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	491.037us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	80.189us	1	1	100.00
		spi_host_csr_rw	4.000s	48.734us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.721us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.701us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	80.189us	1	1	100.00
		spi_host_csr_rw	4.000s	48.734us	1	1	100.00
		spi_host_csr_aliasing	4.000s	32.721us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.701us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	562.393us	1	1	100.00
		spi_host_sec_cm	4.000s	137.603us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	562.393us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	23.717m	69.337ms	1	1	100.00
		TOTAL			26	26	100.00