SRAM_CTRL/MAIN Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	14.470s	1.956ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	205.631us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	35.066us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.620s	1.052ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	32.658us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.150s	372.655us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	35.066us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	32.658us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.834m	7.211ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	50.890s	2.898ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.474m	4.290ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.025m	3.255ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.442m	874.132ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.475m	9.475ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.020s	24.606ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.748m	18.590ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	22.110s	2.109ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.926m	14.415ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.960s	2.489ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.840s	2.992ms	1	1	100.00
		sram_ctrl_throughput_w_readback	11.930s	834.905us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.614m	71.342ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.150s	697.861us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	36.410m	112.932ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.530s	17.465us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.090s	88.201us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.090s	88.201us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	205.631us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	35.066us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	32.658us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	13.601us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	205.631us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	35.066us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	32.658us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	13.601us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.800s	7.887ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
		sram_ctrl_tl_intg_err	3.470s	653.440us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.470s	653.440us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.614m	71.342ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.614m	71.342ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	35.066us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.748m	18.590ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.748m	18.590ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.748m	18.590ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.020s	24.606ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.740s	2.461ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.800s	7.887ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.970s	692.317us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	14.470s	1.956ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	14.470s	1.956ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.748m	18.590ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.020s	24.606ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	14.470s	1.956ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.390s	2.003us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	56.510s	1.071ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.93309025064077510461792662903427148033771710566133126872073981656638261484409
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2003291 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2003291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---