SRAM_CTRL/RET Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	47.520s	2.419ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.530s	47.651us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.420s	11.826us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.940s	51.147us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.740s	19.129us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	52.723us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.420s	11.826us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	19.129us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.210s	527.675us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.330s	140.857us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.725m	7.285ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.623m	16.767ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.670s	4.292ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.747m	5.963ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.260s	1.605ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.893m	51.391ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.730s	4.020ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.436m	12.743ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	37.160s	471.939us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.420s	298.259us	1	1	100.00
		sram_ctrl_throughput_w_readback	6.280s	772.864us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.962m	5.218ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.590s	180.932us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.980m	89.742ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	33.339us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.730s	25.152us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.730s	25.152us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.530s	47.651us	1	1	100.00
		sram_ctrl_csr_rw	1.420s	11.826us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	19.129us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	31.951us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.530s	47.651us	1	1	100.00
		sram_ctrl_csr_rw	1.420s	11.826us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	19.129us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	31.951us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.500s	418.874us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
		sram_ctrl_tl_intg_err	2.250s	337.675us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.250s	337.675us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.962m	5.218ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.962m	5.218ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.420s	11.826us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.893m	51.391ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.893m	51.391ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.893m	51.391ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.260s	1.605ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.170s	98.277us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.500s	418.874us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.870s	47.535us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	47.520s	2.419ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	47.520s	2.419ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.893m	51.391ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.260s	1.605ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	47.520s	2.419ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.440s	4.475us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	39.700s	8.037ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.101143542168752397067902858898247645046154744726735955824586467645101282430020
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4474997 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4474997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---