SYSRST_CTRL Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.120s 2.119ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.660s 2.486ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.570s 2.427ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.270s 2.334ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 10.340s 6.051ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.730s 2.038ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 22.380s 8.890ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.330s 3.113ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 3.580s 2.062ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.730s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.330s 3.113ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.480m 85.029ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.075m 62.583ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.750s 3.099ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.030s 3.470ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.630s 2.526ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.680s 2.156ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.500s 2.924ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.960s 2.661ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.350s 120.569ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.055m 30.905ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 21.450s 11.523ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.350s 2.028ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 6.080s 2.015ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 5.590s 2.496ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 5.590s 2.496ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 10.340s 6.051ms 1 1 100.00
sysrst_ctrl_csr_rw 5.730s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.330s 3.113ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.320s 4.915ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 10.340s 6.051ms 1 1 100.00
sysrst_ctrl_csr_rw 5.730s 2.038ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.330s 3.113ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.320s 4.915ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.700s 42.319ms 1 1 100.00
sysrst_ctrl_tl_intg_err 36.420s 22.193ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 36.420s 22.193ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 9.120s 7.075ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00