UART Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.560s	531.387us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.360s	26.203us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.360s	18.826us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.430s	116.789us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.450s	23.689us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.470s	32.709us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.360s	18.826us	1	1	100.00
		uart_csr_aliasing	1.450s	23.689us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	8.560s	26.690ms	1	1	100.00
V2	parity	uart_smoke	2.560s	531.387us	1	1	100.00
		uart_tx_rx	8.560s	26.690ms	1	1	100.00
V2	parity_error	uart_intr	4.930s	41.218ms	1	1	100.00
		uart_rx_parity_err	10.570s	30.553ms	1	1	100.00
V2	watermark	uart_tx_rx	8.560s	26.690ms	1	1	100.00
		uart_intr	4.930s	41.218ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.450s	81.282ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	26.750s	170.707ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.616m	140.813ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.930s	41.218ms	1	1	100.00
V2	rx_break_err	uart_intr	4.930s	41.218ms	1	1	100.00
V2	rx_timeout	uart_intr	4.930s	41.218ms	1	1	100.00
V2	perf	uart_perf	1.065m	21.729ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.750s	8.613ms	1	1	100.00
V2	line_loopback	uart_loopback	2.750s	8.613ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	40.710s	39.317ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	27.950s	27.571ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.170s	1.253ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	38.910s	6.344ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.055m	38.342ms	1	1	100.00
V2	stress_all	uart_stress_all	45.140s	139.800ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	10.774us	1	1	100.00
V2	intr_test	uart_intr_test	1.520s	66.984us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.090s	300.548us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.090s	300.548us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.360s	26.203us	1	1	100.00
		uart_csr_rw	1.360s	18.826us	1	1	100.00
		uart_csr_aliasing	1.450s	23.689us	1	1	100.00
		uart_same_csr_outstanding	1.560s	111.759us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.360s	26.203us	1	1	100.00
		uart_csr_rw	1.360s	18.826us	1	1	100.00
		uart_csr_aliasing	1.450s	23.689us	1	1	100.00
		uart_same_csr_outstanding	1.560s	111.759us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.550s	221.788us	1	1	100.00
		uart_tl_intg_err	1.930s	151.951us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.930s	151.951us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.230s	2.972ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00