CHIP Simulation Results

Tuesday April 29 2025 18:39:32 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.861m	3.165ms	1	1	100.00
		chip_sw_example_rom	1.256m	2.437ms	1	1	100.00
		chip_sw_example_manufacturer	2.172m	2.505ms	1	1	100.00
		chip_sw_example_concurrency	2.606m	3.402ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.812m	7.696ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.142m	4.018ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.770m	4.260ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.096m	36.854ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	6.117m	8.418ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.096m	36.854ms	1	1	100.00
		chip_csr_rw	3.142m	4.018ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.430s	43.067us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.411m	4.342ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.411m	4.342ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.411m	4.342ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.373m	4.602ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.373m	4.602ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.907m	4.167ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.243m	4.154ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.707m	4.219ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.250m	9.240ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.445m	3.939ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.954m	3.346ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.916m	5.354ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.916m	5.354ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.859m	3.380ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.252m	6.017ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.973m	3.691ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.668m	2.269ms	1	1	100.00
		chip_tap_straps_testunlock0	4.645m	5.290ms	1	1	100.00
		chip_tap_straps_rma	1.416m	2.447ms	1	1	100.00
		chip_tap_straps_prod	1.833m	2.714ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.612m	2.925ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.670m	9.070ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.011m	6.138ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.011m	6.138ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.803m	6.674ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	26.400m	19.547ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.075m	4.632ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.075m	6.326ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.699m	18.426ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.936ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.733m	7.461ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.711m	3.016ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.522m	8.132ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.492m	3.107ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.178m	4.426ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.985m	2.046ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.468m	3.234ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	11.068m	9.477ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.682m	4.727ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.707m	2.866ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.682m	4.727ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.587m	2.530ms	1	1	100.00
		chip_sw_aes_smoketest	3.604m	2.916ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.323m	2.840ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.853m	2.438ms	1	1	100.00
		chip_sw_csrng_smoketest	2.425m	2.881ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.804m	3.194ms	1	1	100.00
		chip_sw_gpio_smoketest	3.228m	2.586ms	1	1	100.00
		chip_sw_hmac_smoketest	3.517m	3.268ms	1	1	100.00
		chip_sw_kmac_smoketest	3.480m	2.921ms	1	1	100.00
		chip_sw_otbn_smoketest	19.204m	10.899ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.992m	6.148ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.010m	5.418ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.091m	2.418ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.412m	3.076ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.263m	2.408ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.797m	2.452ms	1	1	100.00
		chip_sw_uart_smoketest	2.189m	3.422ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.320m	3.335ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.331m	4.207ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.975h	61.281ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	35.785m	14.617ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	37.400s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.307m	3.485ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.103m	3.506ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.712h	53.703ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.735h	56.610ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	45.460s	2.530ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	45.460s	2.530ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.096m	36.854ms	1	1	100.00
		chip_same_csr_outstanding	20.726m	16.277ms	1	1	100.00
		chip_csr_hw_reset	3.812m	7.696ms	1	1	100.00
		chip_csr_rw	3.142m	4.018ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.096m	36.854ms	1	1	100.00
		chip_same_csr_outstanding	20.726m	16.277ms	1	1	100.00
		chip_csr_hw_reset	3.812m	7.696ms	1	1	100.00
		chip_csr_rw	3.142m	4.018ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.750s	639.287us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.870s	40.476us	1	1	100.00
		xbar_smoke_large_delays	54.070s	6.190ms	1	1	100.00
		xbar_smoke_slow_rsp	56.770s	6.300ms	1	1	100.00
		xbar_random_zero_delays	19.630s	348.896us	1	1	100.00
		xbar_random_large_delays	4.328m	46.335ms	1	1	100.00
		xbar_random_slow_rsp	2.708m	17.963ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	19.100s	763.958us	1	1	100.00
		xbar_error_and_unmapped_addr	23.390s	1.078ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	20.390s	241.687us	1	1	100.00
		xbar_error_and_unmapped_addr	23.390s	1.078ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	41.540s	1.553ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.534m	54.498ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	30.680s	1.246ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	54.930s	2.889ms	1	1	100.00
		xbar_stress_all_with_error	2.644m	3.643ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	33.020s	238.251us	1	1	100.00
		xbar_stress_all_with_reset_error	35.320s	149.185us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.785m	14.617ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.858m	26.246ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.442m	15.333ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	25.810s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	15.365s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.504s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	19.646s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	21.022s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.176s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.224s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.381s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.529s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.969s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	14.276s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	14.153s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.450s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	23.216s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.637s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.357s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.491s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.405s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.712s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.497s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.519s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.771s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.029s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.227s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.871s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.165s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.594s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.220s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.227s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.145s		0	1	0.00
		rom_e2e_asm_init_dev	13.446s		0	1	0.00
		rom_e2e_asm_init_prod	13.516s		0	1	0.00
		rom_e2e_asm_init_prod_end	14.205s		0	1	0.00
		rom_e2e_asm_init_rma	12.753s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.943m	14.657ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.704m	15.380ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.087m	15.019ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.335m	15.511ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.827m	34.720ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.827m	34.720ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.327m	3.131ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.936ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.571m	3.272ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.527m	2.239ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.146m	7.982ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.557m	2.863ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.046m	5.224ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.190m	5.581ms	1	1	100.00
		chip_plic_all_irqs_10	5.337m	3.285ms	1	1	100.00
		chip_plic_all_irqs_20	6.527m	4.124ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.062m	2.983ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.674m	13.280ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.030m	3.192ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.749m	3.013ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.469m	10.180ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.616m	6.702ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.837m	6.719ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.943m	8.294ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.225h	255.439ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.183m	3.460ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.992m	6.148ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.183m	3.460ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.918m	8.661ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.918m	8.661ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.787m	6.852ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.016m	4.424ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.272m	6.103ms	1	1	100.00
		chip_sw_aes_idle	2.527m	2.239ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.501m	2.426ms	1	1	100.00
		chip_sw_kmac_idle	2.415m	3.035ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.546m	4.160ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.417m	4.466ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.965m	3.507ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.348m	4.751ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.425m	10.992ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.388m	3.946ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.022m	4.683ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.775m	4.549ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.574m	4.687ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.428m	3.798ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.363m	4.464ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.803m	6.674ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.354m	13.324ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.775m	4.549ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.574m	4.687ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.075m	4.632ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.075m	6.326ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.699m	18.426ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.936ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.733m	7.461ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.711m	3.016ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.522m	8.132ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.492m	3.107ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.178m	4.426ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.985m	2.046ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.594m	2.862ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.247m	4.456ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.633m	6.919ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	43.894m	24.016ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.051m	3.296ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.494m	3.551ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.542m	8.758ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.565m	3.176ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.327m	4.766ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.104m	19.773ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	17.468m	11.400ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.803m	6.674ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.221m	5.210ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.341m	3.501ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.616m	6.702ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.356m	7.910ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.522m	3.394ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.942m	5.799ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.723m	3.097ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.110h	28.088ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.412m	3.360ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.031m	6.809ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.412m	3.360ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.356m	7.910ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.507m	3.388ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.157m	24.338ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.488m	5.377ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.075m	6.326ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.462m	3.498ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.075m	4.632ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.941m	44.166ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.157m	24.338ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.034m	3.088ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.941m	44.166ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.089m	10.344ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.189m	5.242ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.075m	5.494ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.075m	5.494ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.231m	3.305ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.711m	3.016ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.501m	2.426ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.885m	2.715ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	12.685m	6.854ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.123m	4.641ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.644m	4.655ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.917m	5.650ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.186m	4.466ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.522m	8.132ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	14.516m	7.823ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.146m	7.982ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	34.153m	12.204ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.156m	2.721ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.185m	3.043ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.492m	3.107ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.810m	2.890ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.574m	5.449ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.415m	3.035ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.046m	5.224ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.668m	2.269ms	1	1	100.00
		chip_tap_straps_rma	1.416m	2.447ms	1	1	100.00
		chip_tap_straps_prod	1.833m	2.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.084m	2.881ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.949m	10.626ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.668m	4.654ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.941m	44.166ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.373m	3.025ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.732m	6.994ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.717m	7.544ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.271m	7.048ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.829m	9.779ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.148m	7.076ms	1	1	100.00
		chip_prim_tl_access	4.089m	10.344ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.354m	13.324ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.388m	3.946ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.022m	4.683ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.775m	4.549ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.574m	4.687ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.428m	3.798ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.363m	4.464ms	1	1	100.00
		chip_tap_straps_dev	1.668m	2.269ms	1	1	100.00
		chip_tap_straps_rma	1.416m	2.447ms	1	1	100.00
		chip_tap_straps_prod	1.833m	2.714ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.467m	18.100ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.752m	3.114ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.314m	2.592ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.464m	3.954ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.972m	3.510ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.629m	23.760ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.467m	18.100ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	58.495m	48.776ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.801m	48.900ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.200m	9.604ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	55.773m	44.924ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.629m	23.760ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.214m	3.029ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.167m	2.302ms	1	1	100.00
		rom_volatile_raw_unlock	36.563s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	49.032m	16.637ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.699m	18.426ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.272m	6.103ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.272m	6.103ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.272m	6.103ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.027m	3.477ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.157m	24.338ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.027m	3.477ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.128m	4.426ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.638m	2.158ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.157m	24.338ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.027m	3.477ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.314m	9.131ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.128m	4.426ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.638m	2.158ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.805m	4.298ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.084m	2.881ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.373m	3.025ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.732m	6.994ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.717m	7.544ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.271m	7.048ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.071m	5.947ms	1	1	100.00
		chip_prim_tl_access	4.089m	10.344ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.089m	10.344ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.721m	8.010ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.956m	6.786ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.836m	24.486ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.930m	7.081ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.515m	10.049ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.906m	7.411ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.069m	22.620ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.550m	16.317ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.918m	8.661ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.688m	11.514ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.484m	4.137ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.956m	6.786ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.421m	5.116ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.821m	28.028ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.977m	7.508ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.588m	5.633ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.101m	21.491ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	3.170m	2.851ms	0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	15.008m	12.255ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.824m	27.414ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.037m	2.237ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.829m	9.779ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.829m	9.779ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.008m	12.255ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.101m	21.491ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.484m	4.137ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.992m	6.148ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.437m	5.273ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.626m	5.763ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.297m	4.772ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.674m	13.280ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.467m	2.545ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.837m	6.719ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.658m	5.247ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.883m	5.208ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.640m	2.770ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.638m	2.158ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.626m	5.763ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.626m	5.763ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	20.506m	17.825ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.881m	14.170ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.437m	5.273ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.099m	4.976ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.917m	4.868ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.416m	2.447ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.467m	18.100ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.190m	5.581ms	1	1	100.00
		chip_plic_all_irqs_10	5.337m	3.285ms	1	1	100.00
		chip_plic_all_irqs_20	6.527m	4.124ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.938m	3.063ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.258m	2.930ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.785m	14.617ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.450m	7.173ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.411m	3.359ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.393m	3.101ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.735m	2.831ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.128m	4.426ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.178m	4.426ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.194m	6.970ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.076m	8.167ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.148m	7.076ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
		chip_sw_data_integrity_escalation	8.011m	6.138ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	3.170m	2.851ms	0	1	0.00
		chip_sw_sysrst_ctrl_reset	18.015m	22.357ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.545m	3.152ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.385m	3.396ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.509m	4.266ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.015m	22.357ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.015m	22.357ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.341m	2.724ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.341m	2.724ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.289m	6.929ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.827m	34.720ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.331m	3.420ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.187m	3.723ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.361m	3.640ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	6.330m	4.029ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.055m	8.086ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.269h	32.173ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.263m	11.692ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.429m	2.272ms	1	1	100.00
V2		TOTAL			227	275	82.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.579m	2.897ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.655m	2.644ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.391h	71.577ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.043m	3.958ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.367m	11.069ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.689m	10.336ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.312m	11.486ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	42.813s		0	1	0.00
		rom_e2e_jtag_inject_dev	1.271m		0	1	0.00
		rom_e2e_jtag_inject_rma	49.550s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.962s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.826m	4.904ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.272m	3.278ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.683m	7.167ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.459m	8.885ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.794m	2.367ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.608m	4.820ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.756m	2.635ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.668m	5.272ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.290m	6.872ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.115m	5.410ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.008m	12.255ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.367m	11.069ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.689m	10.336ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.312m	11.486ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.770m	4.888ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.048m	5.417ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.326h	38.460ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.326h	38.460ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.175m	3.246ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.373m	4.602ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.246m	19.086ms	1	1	100.00
V3		TOTAL			18	23	78.26
	Unmapped tests	chip_sival_flash_info_access	2.847m	2.907ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.979m	5.456ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.648m	2.216ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.063m	2.941ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.983m	3.657ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.673s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.861m	2.732ms	1	1	100.00
		TOTAL			271	325	83.38

Failure Buckets

• Job returned non-zero exit code has 42 failures:

  • Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

    • 0.chip_sw_pwrmgr_sleep_wake_5_bug.41649733378316354123600310170270263529537441823644151579025872270420187616876
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
        ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
        INFO: Elapsed time: 0.142s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.46809225539835766187389877459358172182685412569887500929796701382508277244724
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (1 packages loaded, 26268 targets configured)
      
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 14.506s, Critical Path: 0.03s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.92213906540084080844859260662466884883978867006397346760211724593605419855843
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (1 packages loaded, 26268 targets configured)
      
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 3.664s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.105305170842751781980794539804306786741041881103974329288578636304961645185279
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26268 targets configured)
      
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 4.336s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.9395936341756551500213734413129490570088014376117770500002373738108859784054
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26268 targets configured)
      
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 9.372s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 37 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.96335749550711930326703836369796264076757889852418265834929556107288535703076
      Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3359.051160 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3359.051160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115157) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.13671847678057943160210952624531265136937369664824494179139754928620612940199
      Line 437, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 5762.828788 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115157) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5762.828788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:

  • Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.

    • 0.chip_sw_pwrmgr_sysrst_ctrl_reset.110174199865688183406511248739442582220763954906753388962893340413752052141194
      Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log

        UVM_ERROR @ 2851.163732 us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
        UVM_INFO @ 2851.163732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:

  • Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.

    • 0.chip_sw_sysrst_ctrl_ec_rst_l.92223177268622194846862108507861455338604528001165774569582223938852477398761
      Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log

        UVM_ERROR @ 2723.884296 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
        UVM_INFO @ 2723.884296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.

    • 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.48297941148113589648586879470657374775641357274573189370588221462145847550481
      Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log

        UVM_ERROR @ 34720.225703 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 34720.225703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 0.chip_sw_alert_test.90021664409014612567230950251914086567220824668051393565096531973202561809634
      Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 2863.070888 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
        UVM_INFO @ 2863.070888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.94561393701882059638726992138805138507678727417065841280956353572161638894831
      Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3012.764312 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 3012.764312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:

  • Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.

    • 0.chip_sw_csrng_fuse_en_sw_app_read_test.63969984053314732261623088054006546046536352425040205186587104858291433732924
      Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_ERROR @ 3393.724570 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
        UVM_INFO @ 3393.724570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32985) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.109960264079564897198169929540053535367626350178336438179163752616415429831127
      Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 2530.023400 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32985) { a_addr: 'h10374  a_data: 'h253795f6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h192f0  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2530.023400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 0.chip_sw_power_idle_load.73807638702348204154152203386550290689280317667144874702239221931697034620989
      Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 3484.759000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3484.759000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_sleep_load has 1 failures.

    • 0.chip_sw_power_sleep_load.27792934765354607198469210780886589682505607772696530218831724121140483463177
      Line 432, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

        UVM_ERROR @ 3505.596000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3505.596000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:

  • Test chip_sw_power_virus has 1 failures.

    • 0.chip_sw_power_virus.71680674721365534917973344466094240419957606713732647194377984587161164101640
      Line 471, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 3958.297636 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 3958.297636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---