ADC_CTRL Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.570s	5.853ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.210s	688.704us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	529.753us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.504m	52.393ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.690s	869.633us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.340s	370.772us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	529.753us	1	1	100.00
		adc_ctrl_csr_aliasing	4.690s	869.633us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	5.108m	169.021ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.413m	488.400ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.307m	325.555ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	12.178m	499.075ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.201m	188.083ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.658m	403.352ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	13.274m	529.147ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.024m	160.932ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.750s	3.726ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	21.810s	25.482ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.166m	107.165ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	3.495m	135.317ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.570s	429.046us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.230s	533.041us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.400s	867.269us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.400s	867.269us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.210s	688.704us	1	1	100.00
		adc_ctrl_csr_rw	1.920s	529.753us	1	1	100.00
		adc_ctrl_csr_aliasing	4.690s	869.633us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.330s	4.349ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.210s	688.704us	1	1	100.00
		adc_ctrl_csr_rw	1.920s	529.753us	1	1	100.00
		adc_ctrl_csr_aliasing	4.690s	869.633us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.330s	4.349ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.350s	4.411ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.400s	8.638ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.400s	8.638ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.140s	6.702ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00