AES/MASKED Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	88.998us	1	1	100.00
V1	smoke	aes_smoke	6.000s	84.022us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	93.876us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	88.621us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	342.433us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	699.953us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	54.090us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	88.621us	1	1	100.00
		aes_csr_aliasing	6.000s	699.953us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	6.000s	84.022us	1	1	100.00
		aes_config_error	5.000s	62.233us	1	1	100.00
		aes_stress	8.000s	245.743us	1	1	100.00
V2	key_length	aes_smoke	6.000s	84.022us	1	1	100.00
		aes_config_error	5.000s	62.233us	1	1	100.00
		aes_stress	8.000s	245.743us	1	1	100.00
V2	back2back	aes_stress	8.000s	245.743us	1	1	100.00
		aes_b2b	12.000s	348.231us	1	1	100.00
V2	backpressure	aes_stress	8.000s	245.743us	1	1	100.00
V2	multi_message	aes_smoke	6.000s	84.022us	1	1	100.00
		aes_config_error	5.000s	62.233us	1	1	100.00
		aes_stress	8.000s	245.743us	1	1	100.00
		aes_alert_reset	5.000s	252.488us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	60.946us	1	1	100.00
		aes_config_error	5.000s	62.233us	1	1	100.00
		aes_alert_reset	5.000s	252.488us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	132.991us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	180.755us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	252.488us	1	1	100.00
V2	stress	aes_stress	8.000s	245.743us	1	1	100.00
V2	sideload	aes_stress	8.000s	245.743us	1	1	100.00
		aes_sideload	5.000s	120.060us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	235.745us	1	1	100.00
V2	stress_all	aes_stress_all	7.000s	108.493us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	81.734us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	71.930us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	71.930us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	93.876us	1	1	100.00
		aes_csr_rw	4.000s	88.621us	1	1	100.00
		aes_csr_aliasing	6.000s	699.953us	1	1	100.00
		aes_same_csr_outstanding	5.000s	95.744us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	93.876us	1	1	100.00
		aes_csr_rw	4.000s	88.621us	1	1	100.00
		aes_csr_aliasing	6.000s	699.953us	1	1	100.00
		aes_same_csr_outstanding	5.000s	95.744us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	86.068us	1	1	100.00
V2S	fault_inject	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	126.084us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	673.476us	1	1	100.00
		aes_tl_intg_err	5.000s	319.510us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	319.510us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	252.488us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	84.022us	1	1	100.00
		aes_stress	8.000s	245.743us	1	1	100.00
		aes_alert_reset	5.000s	252.488us	1	1	100.00
		aes_core_fi	2.250m	10.016ms	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	75.571us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	124.028us	1	1	100.00
		aes_stress	8.000s	245.743us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	245.743us	1	1	100.00
		aes_sideload	5.000s	120.060us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	124.028us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	124.028us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	124.028us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	124.028us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	124.028us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	245.743us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	245.743us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	188.326us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	188.326us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	60.669us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	188.326us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	252.488us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_ctr_fi	5.000s	222.964us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	188.326us	1	1	100.00
		aes_control_fi	5.000s	73.698us	1	1	100.00
		aes_cipher_fi	4.000s	60.669us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.000s	369.192us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.57410448855892846925326789208890317577546110597964957940552208588249415295426
      Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10015530332 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x3716db84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
        UVM_INFO @ 10015530332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.78882395909588120919033372244190351199250907846533228693512476983018908564062
      Line 350, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 369191681 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 369191681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---