EDN Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.840s 40.391us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.930s 20.954us 1 1 100.00
V1 csr_rw edn_csr_rw 1.680s 14.655us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.050s 58.682us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.890s 87.523us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.420s 31.831us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.680s 14.655us 1 1 100.00
edn_csr_aliasing 1.890s 87.523us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.370s 71.955us 1 1 100.00
V2 csrng_commands edn_genbits 2.370s 71.955us 1 1 100.00
V2 genbits edn_genbits 2.370s 71.955us 1 1 100.00
V2 interrupts edn_intr 2.090s 57.013us 1 1 100.00
V2 alerts edn_alert 2.200s 46.846us 1 1 100.00
V2 errs edn_err 2.020s 32.241us 1 1 100.00
V2 disable edn_disable 1.800s 11.770us 1 1 100.00
edn_disable_auto_req_mode 2.120s 60.455us 1 1 100.00
V2 stress_all edn_stress_all 4.440s 234.177us 1 1 100.00
V2 intr_test edn_intr_test 1.770s 33.687us 1 1 100.00
V2 alert_test edn_alert_test 2.050s 61.595us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.650s 106.553us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.650s 106.553us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.930s 20.954us 1 1 100.00
edn_csr_rw 1.680s 14.655us 1 1 100.00
edn_csr_aliasing 1.890s 87.523us 1 1 100.00
edn_same_csr_outstanding 2.120s 106.450us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.930s 20.954us 1 1 100.00
edn_csr_rw 1.680s 14.655us 1 1 100.00
edn_csr_aliasing 1.890s 87.523us 1 1 100.00
edn_same_csr_outstanding 2.120s 106.450us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.710s 344.919us 1 1 100.00
edn_tl_intg_err 2.400s 251.099us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.890s 17.315us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.200s 46.846us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.710s 344.919us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.710s 344.919us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.710s 344.919us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.710s 344.919us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.200s 46.846us 1 1 100.00
edn_sec_cm 4.710s 344.919us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.200s 46.846us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.400s 251.099us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets