35aa874| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 5.000s | 28.601us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 33.920us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 4.000s | 104.329us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 6.000s | 90.171us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 6.000s | 84.285us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 462.168us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 104.329us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 6.000s | 84.285us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 5.000s | 28.601us | 1 | 1 | 100.00 |
| entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 41.000s | 8.143ms | 0 | 1 | 0.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 41.000s | 8.143ms | 0 | 1 | 0.00 |
| V2 | rng_mode | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 31.000s | 863.432us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| entropy_src_intr | 7.000s | 698.062us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 56.059us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 2.133m | 7.325ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 5.000s | 21.777us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 6.000s | 19.267us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 5.000s | 48.468us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 6.000s | 30.403us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 6.000s | 30.403us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 33.920us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 104.329us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 6.000s | 84.285us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 5.000s | 64.705us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 33.920us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 104.329us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 6.000s | 84.285us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 5.000s | 64.705us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 12 | 75.00 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 481.409us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 7.000s | 129.339us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 5.000s | 48.499us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 41.000s | 8.143ms | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 481.409us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 481.409us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 5.000s | 109.411us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 481.409us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 481.409us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 57.072us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 56.059us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 7.000s | 129.339us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 8.000s | 346.806us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 18 | 22 | 81.82 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng_max_rate has 1 failures.
0.entropy_src_rng_max_rate.64695733859659752605630847983788843536276491362863569023473614914245120308017
Line 717, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 863431709 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 863431709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.55536457832074739780661708587080685237733732906969404077203134091498831741194
Line 257, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 346805916 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 346805916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,299): Assertion entropy_control_rd_A has failed has 1 failures:
0.entropy_src_rng.26742742603590249323211350383892421542689704134731627672129640411463571840602
Line 155, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,299): (time 109411186 PS) Assertion tb.dut.entropy_src_csr_assert.entropy_control_rd_A has failed
UVM_ERROR @ 109411186 ps: (entropy_src_csr_assert_fpv.sv:299) [ASSERT FAILED] entropy_control_rd_A
UVM_INFO @ 109411186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.err_code has 1 failures:
0.entropy_src_fw_ov.80125024333904851718597959820668091400929133657102110052187666614384417703206
Line 556, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log
UVM_ERROR @ 8143039833 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1048576 [0x100000] vs 3145728 [0x300000]) reg name: entropy_src_reg_block.err_code
UVM_INFO @ 8143039833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---