HMAC Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.380s 469.956us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.680s 91.535us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.610s 21.116us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.970s 481.731us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.130s 642.429us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.890s 72.118us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.610s 21.116us 1 1 100.00
hmac_csr_aliasing 3.130s 642.429us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 3.680s 494.135us 1 1 100.00
V2 back_pressure hmac_back_pressure 10.200s 959.923us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.440s 356.832us 1 1 100.00
hmac_test_sha384_vectors 7.378m 55.537ms 1 1 100.00
hmac_test_sha512_vectors 19.000s 268.179us 1 1 100.00
hmac_test_hmac256_vectors 7.550s 225.110us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 195.713us 1 1 100.00
hmac_test_hmac512_vectors 10.310s 331.233us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.290s 1.745ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 58.810s 1.893ms 1 1 100.00
V2 error hmac_error 16.180s 1.812ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.157m 154.134ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.380s 469.956us 1 1 100.00
hmac_long_msg 3.680s 494.135us 1 1 100.00
hmac_back_pressure 10.200s 959.923us 1 1 100.00
hmac_datapath_stress 58.810s 1.893ms 1 1 100.00
hmac_burst_wr 11.290s 1.745ms 1 1 100.00
hmac_stress_all 16.216m 95.796ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.380s 469.956us 1 1 100.00
hmac_long_msg 3.680s 494.135us 1 1 100.00
hmac_back_pressure 10.200s 959.923us 1 1 100.00
hmac_datapath_stress 58.810s 1.893ms 1 1 100.00
hmac_wipe_secret 1.157m 154.134ms 1 1 100.00
hmac_test_sha256_vectors 8.440s 356.832us 1 1 100.00
hmac_test_sha384_vectors 7.378m 55.537ms 1 1 100.00
hmac_test_sha512_vectors 19.000s 268.179us 1 1 100.00
hmac_test_hmac256_vectors 7.550s 225.110us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 195.713us 1 1 100.00
hmac_test_hmac512_vectors 10.310s 331.233us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.380s 469.956us 1 1 100.00
hmac_long_msg 3.680s 494.135us 1 1 100.00
hmac_back_pressure 10.200s 959.923us 1 1 100.00
hmac_datapath_stress 58.810s 1.893ms 1 1 100.00
hmac_burst_wr 11.290s 1.745ms 1 1 100.00
hmac_error 16.180s 1.812ms 1 1 100.00
hmac_wipe_secret 1.157m 154.134ms 1 1 100.00
hmac_test_sha256_vectors 8.440s 356.832us 1 1 100.00
hmac_test_sha384_vectors 7.378m 55.537ms 1 1 100.00
hmac_test_sha512_vectors 19.000s 268.179us 1 1 100.00
hmac_test_hmac256_vectors 7.550s 225.110us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 195.713us 1 1 100.00
hmac_test_hmac512_vectors 10.310s 331.233us 1 1 100.00
hmac_stress_all 16.216m 95.796ms 1 1 100.00
V2 stress_all hmac_stress_all 16.216m 95.796ms 1 1 100.00
V2 alert_test hmac_alert_test 1.520s 13.195us 1 1 100.00
V2 intr_test hmac_intr_test 1.420s 34.005us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.320s 128.527us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.320s 128.527us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.680s 91.535us 1 1 100.00
hmac_csr_rw 1.610s 21.116us 1 1 100.00
hmac_csr_aliasing 3.130s 642.429us 1 1 100.00
hmac_same_csr_outstanding 2.700s 421.311us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.680s 91.535us 1 1 100.00
hmac_csr_rw 1.610s 21.116us 1 1 100.00
hmac_csr_aliasing 3.130s 642.429us 1 1 100.00
hmac_same_csr_outstanding 2.700s 421.311us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.570s 35.857us 1 1 100.00
hmac_tl_intg_err 2.880s 174.282us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.880s 174.282us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.380s 469.956us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.740s 142.261us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.002m 4.537ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.630s 22.052us 1 1 100.00
TOTAL 28 28 100.00