I2C Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: `35aa874`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.640s	3.362ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.200s	7.032ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.470s	110.544us	1	1	100.00
V1	csr_rw	i2c_csr_rw	2.120s	46.644us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.460s	982.063us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.390s	42.355us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.930s	37.296us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.120s	46.644us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.355us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.450s	356.390us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	8.961m	22.968ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	26.930s	30.415ms	1	1	100.00
V2	host_override	i2c_host_override	1.640s	19.870us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	51.300s	17.053ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	31.000s	7.716ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.970s	182.035us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.110s	1.206ms	1	1	100.00
		i2c_host_fifo_reset_rx	9.470s	992.360us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.130m	3.503ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.820s	981.463us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.510s	134.135us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.720s	1.914ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	6.550m	88.399ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.000s	510.665us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	21.740s	3.109ms	1	1	100.00
		i2c_target_intr_smoke	3.730s	536.997us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.070s	168.466us	1	1	100.00
		i2c_target_fifo_reset_tx	2.100s	431.294us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.229m	27.272ms	1	1	100.00
		i2c_target_stress_rd	21.740s	3.109ms	1	1	100.00
		i2c_target_intr_stress_wr	1.518m	21.549ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.490s	14.797ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.000s	239.912us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.720s	918.436us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	23.420s	10.172ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.280s	894.135us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.250s	156.619us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	26.930s	30.415ms	1	1	100.00
		i2c_host_perf_precise	1.214m	6.231ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.820s	981.463us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.420s	252.493us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.620s	970.583us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.050s	1.210ms	1	1	100.00
		i2c_target_nack_txstretch	2.410s	151.353us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	11.310s	349.733us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.550s	1.023ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.600s	161.989us	1	1	100.00
V2	intr_test	i2c_intr_test	1.670s	17.762us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.930s	112.238us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.930s	112.238us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.470s	110.544us	1	1	100.00
		i2c_csr_rw	2.120s	46.644us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.355us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	239.781us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.470s	110.544us	1	1	100.00
		i2c_csr_rw	2.120s	46.644us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.355us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	239.781us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.170s	54.816us	1	1	100.00
		i2c_sec_cm	2.100s	212.698us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.170s	54.816us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.770s	109.362us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.620s	66.900us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.590s	3.291ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.34861966318614970176732268748951634009148124057882015420654812066139992983650
Line 132, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 22968391507 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4537740

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.41496538061401721879692398709440062945057607001785290353754456882658946852768
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  66900303 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66900303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.100352160299450642646700959090098543742844096130964742354899424659735314923780
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10172284324 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10172284324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.45847856026687379154210569526642270742707000425539719821917842688313892334175
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109362486 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 109362486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.99937987806487669462006047668823900080529685342135984732705676501808490219527
    Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3291014521 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
  UVM_INFO @ 3291014521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```