KMAC/MASKED Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	43.040s	4.569ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.940s	66.919us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.160s	47.745us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.830s	1.366ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.320s	507.135us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.060s	19.762us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.160s	47.745us	1	1	100.00
		kmac_csr_aliasing	6.320s	507.135us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.750s	16.777us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.050s	37.000us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.655m	65.515ms	1	1	100.00
V2	burst_write	kmac_burst_write	16.557m	12.963ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.130s	11.305ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.800s	4.410ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.580s	3.278ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.370s	5.377ms	1	1	100.00
		kmac_test_vectors_shake_128	2.382m	28.868ms	1	1	100.00
		kmac_test_vectors_shake_256	4.675m	11.205ms	1	1	100.00
		kmac_test_vectors_kmac	3.340s	63.779us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.920s	96.314us	1	1	100.00
V2	sideload	kmac_sideload	4.285m	17.806ms	1	1	100.00
V2	app	kmac_app	4.905m	12.675ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.823m	10.541ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.660s	236.053us	1	1	100.00
V2	error	kmac_error	2.283m	11.972ms	1	1	100.00
V2	key_error	kmac_key_error	3.420s	510.686us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.770s	899.404us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.930s	21.874us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.700s	455.786us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.042m	14.990ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	9.040s	248.464us	1	1	100.00
V2	stress_all	kmac_stress_all	5.630m	9.017ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.600s	65.393us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	31.381us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.560s	561.005us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.560s	561.005us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.940s	66.919us	1	1	100.00
		kmac_csr_rw	2.160s	47.745us	1	1	100.00
		kmac_csr_aliasing	6.320s	507.135us	1	1	100.00
		kmac_same_csr_outstanding	3.400s	139.318us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.940s	66.919us	1	1	100.00
		kmac_csr_rw	2.160s	47.745us	1	1	100.00
		kmac_csr_aliasing	6.320s	507.135us	1	1	100.00
		kmac_same_csr_outstanding	3.400s	139.318us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.870s	76.459us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.870s	76.459us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.870s	76.459us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.870s	76.459us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.810s	367.286us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.020s	5.121ms	1	1	100.00
		kmac_tl_intg_err	1.780s	8.329us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.780s	8.329us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	9.040s	248.464us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	43.040s	4.569ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.285m	17.806ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.870s	76.459us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.020s	5.121ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.020s	5.121ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.020s	5.121ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	43.040s	4.569ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	9.040s	248.464us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.020s	5.121ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.178m	3.230ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	43.040s	4.569ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.509m	12.320ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.33444887240170814352449207000588057344663183619941584064673559389932592407801
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @   8329263 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @   8329263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---