OTBN Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	79.163us	1	1	100.00
V1	single_binary	otbn_single	15.000s	89.998us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	32.151us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	21.642us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	72.747us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	67.213us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	22.190us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	21.642us	1	1	100.00
		otbn_csr_aliasing	6.000s	67.213us	1	1	100.00
V1	mem_walk	otbn_mem_walk	16.000s	713.956us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	1.396ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	22.000s	880.545us	1	1	100.00
V2	multi_error	otbn_multi_err	50.000s	186.999us	1	1	100.00
V2	back_to_back	otbn_multi	27.000s	86.547us	0	1	0.00
V2	stress_all	otbn_stress_all	17.000s	60.555us	1	1	100.00
V2	lc_escalation	otbn_escalate	14.000s	28.516us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	18.055us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	11.000s	36.960us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	47.942us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	38.833us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	20.000s	304.119us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	20.000s	304.119us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	32.151us	1	1	100.00
		otbn_csr_rw	7.000s	21.642us	1	1	100.00
		otbn_csr_aliasing	6.000s	67.213us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	18.848us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	32.151us	1	1	100.00
		otbn_csr_rw	7.000s	21.642us	1	1	100.00
		otbn_csr_aliasing	6.000s	67.213us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	18.848us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	9.000s	30.545us	1	1	100.00
		otbn_dmem_err	11.000s	46.468us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	67.044us	1	1	100.00
		otbn_controller_ispr_rdata_err	13.000s	49.241us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	118.264us	1	1	100.00
		otbn_urnd_err	13.000s	48.476us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	48.124us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	43.579us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	20.999us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	10.000s	48.393us	0	1	0.00
		otbn_tl_intg_err	27.000s	95.947us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	56.000s	114.699us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	79.163us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	46.468us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	30.545us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	27.000s	95.947us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	14.000s	28.516us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	30.545us	1	1	100.00
		otbn_dmem_err	11.000s	46.468us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.055us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.124us	1	1	100.00
		otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	30.545us	1	1	100.00
		otbn_dmem_err	11.000s	46.468us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.055us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.124us	1	1	100.00
		otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	14.000s	28.516us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	30.545us	1	1	100.00
		otbn_dmem_err	11.000s	46.468us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	18.055us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	48.124us	1	1	100.00
		otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	52.040us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	151.604us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.567m	323.666us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.567m	323.666us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	65.954us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	124.407us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	21.231us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	21.231us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	23.432us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	27.000s	86.547us	0	1	0.00
V2S	sec_cm_ctrl_flow_count	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	28.000s	464.041us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	15.000s	89.998us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.000s	48.393us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.800m	1.914ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.24177112633061299663888406980446479381766908879815562335450668324741661890870
      Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        UVM_FATAL @  86547215 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  86547215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.67191573074363321986455261759253046688658418386276597280797266903069382249499
      Line 185, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1913815967 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 1913815967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.85091415681076010451336465515417768459018041343541140552082358712428112696809
      Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 48393070 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 48393070 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  48393070 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  48393070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---