PATTGEN Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: `35aa874`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	395.667us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	10.000s	16.298us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	9.000s	24.943us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	9.000s	405.282us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	6.000s	102.570us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	48.146us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	9.000s	24.943us	1	1	100.00
		pattgen_csr_aliasing	6.000s	102.570us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	11.000s	716.869us	1	1	100.00
V2	error	pattgen_error	4.000s	54.325us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	41.957us	1	1	100.00
V2	intr_test	pattgen_intr_test	11.000s	14.030us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	11.000s	119.408us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	11.000s	119.408us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	10.000s	16.298us	1	1	100.00
		pattgen_csr_rw	9.000s	24.943us	1	1	100.00
		pattgen_csr_aliasing	6.000s	102.570us	1	1	100.00
		pattgen_same_csr_outstanding	6.000s	28.642us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	10.000s	16.298us	1	1	100.00
		pattgen_csr_rw	9.000s	24.943us	1	1	100.00
		pattgen_csr_aliasing	6.000s	102.570us	1	1	100.00
		pattgen_same_csr_outstanding	6.000s	28.642us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	11.000s	90.786us	1	1	100.00
		pattgen_sec_cm	4.000s	67.304us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	11.000s	90.786us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	13.000s	1.540ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	5.000s	50.808us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

Job timed out after * minutes has 2 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.6397007017619343675515922035261102454513493888250110553954988232759132387093
    Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.56328890602973304944742691031664006252262823949918351886164630012890951462834
    Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  Job timed out after 180 minutes
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.80874878787890357559890389650459803960234686934731401784589929317708144710348
Line 163, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 227054940 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 227056346 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 227056346 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 227142768 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]