ROM_CTRL/32KB Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.670s 417.630us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.490s 194.664us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.240s 209.246us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.550s 576.165us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.280s 128.667us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.620s 133.116us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.240s 209.246us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 128.667us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.450s 169.059us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.000s 1.225ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.130s 578.743us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.160s 1.874ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.230s 1.048ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.650s 533.563us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.950s 292.557us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.950s 292.557us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.490s 194.664us 1 1 100.00
rom_ctrl_csr_rw 4.240s 209.246us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 128.667us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 372.626us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.490s 194.664us 1 1 100.00
rom_ctrl_csr_rw 4.240s 209.246us 1 1 100.00
rom_ctrl_csr_aliasing 4.280s 128.667us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.800s 372.626us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.570s 5.635ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
rom_ctrl_tl_intg_err 40.960s 1.718ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.670s 417.630us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.670s 417.630us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.670s 417.630us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 40.960s 1.718ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 8.230s 1.048ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.570s 5.635ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.505m 367.771us 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.409m 6.221ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets