ROM_CTRL/64KB Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.820s 301.048us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.020s 293.498us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.450s 288.500us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.090s 699.739us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 9.910s 1.020ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.250s 1.066ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.450s 288.500us 1 1 100.00
rom_ctrl_csr_aliasing 9.910s 1.020ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.800s 1.117ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.050s 535.870us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.940s 300.880us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.130s 1.575ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.450s 562.231us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.900s 699.012us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.110s 295.436us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.110s 295.436us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.020s 293.498us 1 1 100.00
rom_ctrl_csr_rw 7.450s 288.500us 1 1 100.00
rom_ctrl_csr_aliasing 9.910s 1.020ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.060s 649.694us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.020s 293.498us 1 1 100.00
rom_ctrl_csr_rw 7.450s 288.500us 1 1 100.00
rom_ctrl_csr_aliasing 9.910s 1.020ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.060s 649.694us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 34.650s 16.546ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
rom_ctrl_tl_intg_err 1.104m 1.570ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.820s 301.048us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.820s 301.048us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.820s 301.048us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.104m 1.570ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 14.450s 562.231us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 34.650s 16.546ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.263m 2.524ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.183m 10.903ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets