RV_TIMER Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.500s	11.847us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.580s	16.856us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.670s	11.130us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.230s	197.650us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.640s	53.181us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.670s	39.945us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.670s	11.130us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	53.181us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	13.440s	86.473ms	1	1	100.00
V2	disabled	rv_timer_disabled	3.451m	745.741ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	53.910s	216.168ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	53.910s	216.168ms	1	1	100.00
V2	stress	rv_timer_stress_all	5.640m	304.391ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.850s	35.501us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.550s	11.291us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.720s	525.600us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.720s	525.600us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.580s	16.856us	1	1	100.00
		rv_timer_csr_rw	1.670s	11.130us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	53.181us	1	1	100.00
		rv_timer_same_csr_outstanding	1.780s	37.517us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.580s	16.856us	1	1	100.00
		rv_timer_csr_rw	1.670s	11.130us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	53.181us	1	1	100.00
		rv_timer_same_csr_outstanding	1.780s	37.517us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.780s	67.556us	1	1	100.00
		rv_timer_tl_intg_err	1.840s	102.846us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.840s	102.846us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	51.930s	19.054ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	17	100.00