SPI_DEVICE/1R1W Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.924m	12.178ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.070s	72.729us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	39.283us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.940s	1.802ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.080s	794.739us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.370s	325.758us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	39.283us	1	1	100.00
		spi_device_csr_aliasing	11.080s	794.739us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	31.380us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.900s	29.054us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.670s	59.893us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.720s	1.219us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.470s	1.494us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.420s	171.482us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.420s	171.482us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.480s	1.336ms	1	1	100.00
		spi_device_tpm_sts_read	1.690s	45.510us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.680s	1.539ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.570s	483.927us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.830s	618.787us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.830s	618.787us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.760s	295.846us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.760s	295.846us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.760s	295.846us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.760s	295.846us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.760s	295.846us	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.240s	2.759ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	33.240s	16.954ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	33.240s	16.954ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	33.240s	16.954ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.090s	271.489us	1	1	100.00
		spi_device_read_buffer_direct	11.710s	1.821ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	33.240s	16.954ms	1	1	100.00
		spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	27.660s	41.952ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.750s	793.974us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.750s	793.974us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.924m	12.178ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.030s	2.006ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.678m	31.962ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.160s	11.181us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.870s	122.521us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.570s	111.271us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.570s	111.271us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.070s	72.729us	1	1	100.00
		spi_device_csr_rw	2.800s	39.283us	1	1	100.00
		spi_device_csr_aliasing	11.080s	794.739us	1	1	100.00
		spi_device_same_csr_outstanding	3.170s	108.126us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.070s	72.729us	1	1	100.00
		spi_device_csr_rw	2.800s	39.283us	1	1	100.00
		spi_device_csr_aliasing	11.080s	794.739us	1	1	100.00
		spi_device_same_csr_outstanding	3.170s	108.126us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.960s	189.249us	1	1	100.00
		spi_device_tl_intg_err	5.650s	104.945us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.650s	104.945us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.122m	77.563ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.69999233002610785025070558842144519356876566776507867184610339222369245265584
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1021392 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[38])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1021392 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1021392 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[934])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.184190131765209721142385437213320244015967300930794365075354153184123418663
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    883881 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    883881 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    966881 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x43e101 [10000111110000100000001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    966881 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x43e101 [10000111110000100000001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])