SPI_DEVICE/2P Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.014m	25.833ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.890s	237.874us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.680s	160.766us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.510s	6.072ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.560s	1.021ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.360s	53.560us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.680s	160.766us	1	1	100.00
		spi_device_csr_aliasing	10.560s	1.021ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	35.317us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	52.943us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	14.070us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	85.780us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.520s	1.713us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.550s	21.265us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.550s	21.265us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.620s	5.564ms	1	1	100.00
		spi_device_tpm_sts_read	1.540s	140.501us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.250s	6.509ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	7.030s	543.074us	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.540s	516.003us	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.540s	516.003us	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	9.560s	2.379ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	9.560s	2.379ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.560s	2.379ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	9.560s	2.379ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	9.560s	2.379ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.350s	3.440ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	14.910s	6.978ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	14.910s	6.978ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	14.910s	6.978ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	15.170s	2.602ms	1	1	100.00
		spi_device_read_buffer_direct	3.330s	187.816us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	14.910s	6.978ms	1	1	100.00
		spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	37.750s	3.023ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.980s	414.929us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.980s	414.929us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.014m	25.833ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.345m	47.978ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.561m	14.038ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.500s	28.125us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.640s	91.587us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.320s	211.846us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.320s	211.846us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.890s	237.874us	1	1	100.00
		spi_device_csr_rw	2.680s	160.766us	1	1	100.00
		spi_device_csr_aliasing	10.560s	1.021ms	1	1	100.00
		spi_device_same_csr_outstanding	3.040s	408.928us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.890s	237.874us	1	1	100.00
		spi_device_csr_rw	2.680s	160.766us	1	1	100.00
		spi_device_csr_aliasing	10.560s	1.021ms	1	1	100.00
		spi_device_same_csr_outstanding	3.040s	408.928us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.890s	150.698us	1	1	100.00
		spi_device_tl_intg_err	16.830s	993.682us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.830s	993.682us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.256m	23.456ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.89843317648998354418044885362021258791147981785010432301231911049094818845172
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    875722 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    875722 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    965722 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x6049dc [11000000100100111011100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    965722 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)