SPI_HOST Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 1.050m 10.044ms 1 1 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 13.000s 18.883us 1 1 100.00
V1 csr_rw spi_host_csr_rw 13.000s 27.443us 1 1 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 13.000s 202.574us 1 1 100.00
V1 csr_aliasing spi_host_csr_aliasing 12.000s 51.732us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 12.000s 119.611us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 13.000s 27.443us 1 1 100.00
spi_host_csr_aliasing 12.000s 51.732us 1 1 100.00
V1 mem_walk spi_host_mem_walk 13.000s 29.903us 1 1 100.00
V1 mem_partial_access spi_host_mem_partial_access 12.000s 33.744us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 performance spi_host_performance 4.000s 135.601us 1 1 100.00
V2 error_event_intr spi_host_overflow_underflow 8.000s 501.228us 1 1 100.00
spi_host_error_cmd 4.000s 18.217us 1 1 100.00
spi_host_event 34.000s 1.260ms 1 1 100.00
V2 clock_rate spi_host_speed 6.000s 470.624us 1 1 100.00
V2 speed spi_host_speed 6.000s 470.624us 1 1 100.00
V2 chip_select_timing spi_host_speed 6.000s 470.624us 1 1 100.00
V2 sw_reset spi_host_sw_reset 14.000s 421.424us 1 1 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 279.921us 1 1 100.00
V2 cpol_cpha spi_host_speed 6.000s 470.624us 1 1 100.00
V2 full_cycle spi_host_speed 6.000s 470.624us 1 1 100.00
V2 duplex spi_host_smoke 1.050m 10.044ms 1 1 100.00
V2 tx_rx_only spi_host_smoke 1.050m 10.044ms 1 1 100.00
V2 stress_all spi_host_stress_all 53.000s 1.516ms 1 1 100.00
V2 spien spi_host_spien 8.000s 654.583us 1 1 100.00
V2 stall spi_host_status_stall 4.483m 21.065ms 1 1 100.00
V2 Idlecsbactive spi_host_idlecsbactive 5.000s 48.517us 1 1 100.00
V2 data_fifo_status spi_host_overflow_underflow 8.000s 501.228us 1 1 100.00
V2 alert_test spi_host_alert_test 4.000s 41.932us 1 1 100.00
V2 intr_test spi_host_intr_test 14.000s 20.030us 1 1 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 14.000s 37.582us 1 1 100.00
V2 tl_d_illegal_access spi_host_tl_errors 14.000s 37.582us 1 1 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 13.000s 18.883us 1 1 100.00
spi_host_csr_rw 13.000s 27.443us 1 1 100.00
spi_host_csr_aliasing 12.000s 51.732us 1 1 100.00
spi_host_same_csr_outstanding 12.000s 118.735us 1 1 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 13.000s 18.883us 1 1 100.00
spi_host_csr_rw 13.000s 27.443us 1 1 100.00
spi_host_csr_aliasing 12.000s 51.732us 1 1 100.00
spi_host_same_csr_outstanding 12.000s 118.735us 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err spi_host_tl_intg_err 14.000s 99.751us 1 1 100.00
spi_host_sec_cm 4.000s 136.595us 1 1 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 14.000s 99.751us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_host_upper_range_clkdiv 0 1 0.00
TOTAL 25 26 96.15

Failure Buckets