SRAM_CTRL/RET Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.770s	160.334us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.590s	40.767us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	24.559us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.950s	236.583us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	13.023us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.130s	179.909us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	24.559us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	13.023us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.170s	349.836us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.420s	379.339us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.330m	7.108ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.041m	3.539ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	1.041m	13.895ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.057m	14.328ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.740s	894.208us	1	1	100.00
V2	executable	sram_ctrl_executable	3.654m	27.706ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	22.980s	870.855us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.187m	13.726ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	27.080s	109.924us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	47.050s	155.748us	1	1	100.00
		sram_ctrl_throughput_w_readback	18.800s	896.645us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.560m	69.912ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.790s	40.072us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.442m	51.443ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.830s	81.537us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.150s	170.140us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.150s	170.140us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.590s	40.767us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	24.559us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	13.023us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.910s	21.157us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.590s	40.767us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	24.559us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	13.023us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.910s	21.157us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.220s	478.505us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
		sram_ctrl_tl_intg_err	2.880s	206.641us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.880s	206.641us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.560m	69.912ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.560m	69.912ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	24.559us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.654m	27.706ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.654m	27.706ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.654m	27.706ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.740s	894.208us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.760s	37.509us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.220s	478.505us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.990s	68.870us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.770s	160.334us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.770s	160.334us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.654m	27.706ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.740s	894.208us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.770s	160.334us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.100s	1.751us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.678m	4.399ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.61614459302715627673693531420029286427961956680756477687043958399672512873154
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1751031 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1751031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---