SYSRST_CTRL Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.300s 2.113ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.620s 2.497ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.770s 2.412ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.300s 2.245ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.040s 6.057ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.030s 2.074ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 32.120s 41.538ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.680s 2.247ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 5.550s 2.089ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.030s 2.074ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.247ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.785m 108.256ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.915m 67.235ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.640s 3.248ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.820s 3.337ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.750s 2.524ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.130s 2.184ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.600s 2.501ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.720s 2.611ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.058m 856.215ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 11.160s 30.304ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 13.190s 14.325ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.380s 2.017ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.130s 2.065ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.320s 2.059ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.320s 2.059ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.040s 6.057ms 1 1 100.00
sysrst_ctrl_csr_rw 2.030s 2.074ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.247ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.370s 9.692ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.040s 6.057ms 1 1 100.00
sysrst_ctrl_csr_rw 2.030s 2.074ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.247ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 20.370s 9.692ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 21.440s 42.120ms 1 1 100.00
sysrst_ctrl_tl_intg_err 26.520s 22.295ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 26.520s 22.295ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 11.550s 4.878ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00