UART Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	18.160s	6.292ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.370s	42.344us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.470s	21.015us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.030s	104.300us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.490s	38.898us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.630s	86.055us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.470s	21.015us	1	1	100.00
		uart_csr_aliasing	1.490s	38.898us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.284m	70.520ms	1	1	100.00
V2	parity	uart_smoke	18.160s	6.292ms	1	1	100.00
		uart_tx_rx	1.284m	70.520ms	1	1	100.00
V2	parity_error	uart_intr	31.110s	50.938ms	1	1	100.00
		uart_rx_parity_err	19.660s	90.726ms	1	1	100.00
V2	watermark	uart_tx_rx	1.284m	70.520ms	1	1	100.00
		uart_intr	31.110s	50.938ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.410s	86.804ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	28.520s	23.321ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	37.510s	28.874ms	1	1	100.00
V2	rx_frame_err	uart_intr	31.110s	50.938ms	1	1	100.00
V2	rx_break_err	uart_intr	31.110s	50.938ms	1	1	100.00
V2	rx_timeout	uart_intr	31.110s	50.938ms	1	1	100.00
V2	perf	uart_perf	6.418m	19.436ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.610s	4.857ms	1	1	100.00
V2	line_loopback	uart_loopback	8.610s	4.857ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	7.690s	22.041ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.250s	3.203ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.960s	4.109ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.520s	2.799ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.224m	141.213ms	1	1	100.00
V2	stress_all	uart_stress_all	1.516m	302.880ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	11.192us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	13.669us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.330s	1.659ms	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.330s	1.659ms	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.370s	42.344us	1	1	100.00
		uart_csr_rw	1.470s	21.015us	1	1	100.00
		uart_csr_aliasing	1.490s	38.898us	1	1	100.00
		uart_same_csr_outstanding	1.410s	16.528us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.370s	42.344us	1	1	100.00
		uart_csr_rw	1.470s	21.015us	1	1	100.00
		uart_csr_aliasing	1.490s	38.898us	1	1	100.00
		uart_same_csr_outstanding	1.410s	16.528us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.710s	150.300us	1	1	100.00
		uart_tl_intg_err	1.870s	99.594us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.870s	99.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.220s	6.740ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00