CHIP Simulation Results

Wednesday April 30 2025 20:21:06 UTC

GitHub Revision: `35aa874`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.026m	2.715ms	1	1	100.00
		chip_sw_example_rom	1.180m	2.568ms	1	1	100.00
		chip_sw_example_manufacturer	2.302m	2.835ms	1	1	100.00
		chip_sw_example_concurrency	2.693m	2.896ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.739m	4.772ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.217m	4.543ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.629m	5.378ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.058h	30.943ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.006m	2.692ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.058h	30.943ms	1	1	100.00
		chip_csr_rw	3.217m	4.543ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.520s	240.653us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.269m	3.459ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.269m	3.459ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.269m	3.459ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.761m	3.620ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.761m	3.620ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.521m	4.183ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.583m	4.529ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.168m	4.764ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.089m	8.477ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.375m	13.413ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.307m	4.637ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.574m	4.861ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.574m	4.861ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.569m	3.304ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.903m	4.587ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.932m	3.982ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.396m	2.878ms	1	1	100.00
		chip_tap_straps_testunlock0	4.726m	5.197ms	1	1	100.00
		chip_tap_straps_rma	4.767m	6.449ms	1	1	100.00
		chip_tap_straps_prod	8.005m	8.345ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.346m	2.776ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.034m	8.897ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.744m	5.222ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.744m	5.222ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.159m	8.222ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	17.907m	12.803ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.070m	4.072ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.289m	5.427ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.747m	18.473ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.473m	3.002ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.692m	5.730ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.723m	3.403ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.820m	9.219ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.554m	3.048ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.531m	4.789ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.820m	2.759ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.578m	2.901ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.431m	6.011ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.921m	5.522ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.374m	2.392ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.921m	5.522ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.051m	3.118ms	1	1	100.00
		chip_sw_aes_smoketest	2.029m	2.416ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.823m	3.514ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.475m	2.738ms	1	1	100.00
		chip_sw_csrng_smoketest	2.872m	2.679ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.979m	3.239ms	1	1	100.00
		chip_sw_gpio_smoketest	3.756m	2.842ms	1	1	100.00
		chip_sw_hmac_smoketest	3.166m	3.445ms	1	1	100.00
		chip_sw_kmac_smoketest	2.475m	3.056ms	1	1	100.00
		chip_sw_otbn_smoketest	19.114m	9.946ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.365m	5.527ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.433m	4.917ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.506m	3.471ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.433m	3.044ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.234m	2.693ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.466m	2.503ms	1	1	100.00
		chip_sw_uart_smoketest	2.458m	2.620ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.661m	3.293ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.082m	4.219ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.066h	61.153ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.675m	15.009ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.292m	4.329ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.370m	3.586ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.737m	2.433ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.760h	54.108ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.829h	57.044ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	50.960s	2.964ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	50.960s	2.964ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.058h	30.943ms	1	1	100.00
		chip_same_csr_outstanding	22.461m	15.651ms	1	1	100.00
		chip_csr_hw_reset	2.739m	4.772ms	1	1	100.00
		chip_csr_rw	3.217m	4.543ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.058h	30.943ms	1	1	100.00
		chip_same_csr_outstanding	22.461m	15.651ms	1	1	100.00
		chip_csr_hw_reset	2.739m	4.772ms	1	1	100.00
		chip_csr_rw	3.217m	4.543ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	15.590s	248.987us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.520s	45.245us	1	1	100.00
		xbar_smoke_large_delays	41.690s	7.016ms	1	1	100.00
		xbar_smoke_slow_rsp	55.820s	5.837ms	1	1	100.00
		xbar_random_zero_delays	28.030s	548.870us	1	1	100.00
		xbar_random_large_delays	3.222m	32.933ms	1	1	100.00
		xbar_random_slow_rsp	42.160s	4.543ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.620s	252.189us	1	1	100.00
		xbar_error_and_unmapped_addr	15.460s	212.087us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	26.590s	1.399ms	1	1	100.00
		xbar_error_and_unmapped_addr	15.460s	212.087us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.127m	2.664ms	1	1	100.00
		xbar_access_same_device_slow_rsp	3.536m	25.460ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.490s	458.161us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	36.500s	1.979ms	1	1	100.00
		xbar_stress_all_with_error	4.348m	15.227ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.667m	2.374ms	1	1	100.00
		xbar_stress_all_with_reset_error	3.532m	3.656ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.675m	15.009ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.811m	28.627ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.426m	15.317ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.429m	11.668ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.873m	16.054ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.088m	15.740ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.385m	15.385ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.681m	14.361ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.420s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.180s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	32.250s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.870s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.570s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	29.520s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.750s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.520s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.360s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.780s	10.300us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.280s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.470s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.360s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.610s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.670s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.180s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	28.580s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.520s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.530s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.710s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	29.380s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.310s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	28.760s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.130s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.790s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.050m	10.738ms	1	1	100.00
		rom_e2e_asm_init_dev	38.038m	15.103ms	1	1	100.00
		rom_e2e_asm_init_prod	38.128m	15.749ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.265m	14.953ms	1	1	100.00
		rom_e2e_asm_init_rma	35.264m	15.613ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.898m	14.847ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.509m	14.736ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.086m	15.550ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.793m	16.064ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.148m	34.601ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.148m	34.601ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.400m	2.258ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.473m	3.002ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.663m	3.093ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.946m	2.324ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	19.072m	9.901ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.768m	2.442ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.728m	4.966ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.567m	5.303ms	1	1	100.00
		chip_plic_all_irqs_10	3.595m	3.667ms	1	1	100.00
		chip_plic_all_irqs_20	5.057m	4.167ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.170m	3.606ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.099m	9.181ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.366m	4.117ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.373m	3.010ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.575m	9.499ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.523m	8.470ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.179m	6.824ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.895m	7.896ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.160h	254.694ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.719m	4.174ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.365m	5.527ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.719m	4.174ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.664m	6.678ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.664m	6.678ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.793m	6.682ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.148m	5.673ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.523m	5.865ms	1	1	100.00
		chip_sw_aes_idle	1.946m	2.324ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.674m	3.518ms	1	1	100.00
		chip_sw_kmac_idle	1.706m	3.255ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.103m	3.264ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.525m	3.826ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.796m	4.560ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.225m	4.637ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.384m	12.732ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.210m	3.216ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.924m	4.272ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.486m	3.650ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.586m	4.713ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.912m	3.885ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.975m	4.678ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.159m	8.222ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.925m	10.832ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.486m	3.650ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.586m	4.713ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.070m	4.072ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.289m	5.427ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.747m	18.473ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.473m	3.002ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.692m	5.730ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.723m	3.403ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.820m	9.219ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.554m	3.048ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.531m	4.789ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.820m	2.759ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.747m	2.647ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.008m	4.648ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.501m	6.537ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.139m	23.589ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.179m	2.945ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.315m	2.938ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.956m	7.694ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.746m	2.616ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.333m	5.096ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.338m	17.441ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	24.676m	15.302ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.159m	8.222ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.679m	4.198ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.482m	3.145ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.523m	8.470ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.365m	7.412ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.581m	2.917ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.006m	5.358ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.892m	2.873ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.488h	40.103ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.764m	2.785ms	1	1	100.00
		chip_sw_edn_entropy_reqs	7.740m	5.620ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.764m	2.785ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.365m	7.412ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.159m	2.813ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.979m	19.894ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.025m	5.726ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.289m	5.427ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.898m	4.328ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.070m	4.072ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.629m	43.047ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.979m	19.894ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.292m	3.888ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.629m	43.047ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.216m	7.868ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.725m	5.178ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	4.477m	5.145ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	4.477m	5.145ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.878m	2.814ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.723m	3.403ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.674m	3.518ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.032m	2.921ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	12.482m	7.532ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.291m	5.121ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.865m	3.953ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.912m	5.313ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.320m	3.684ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.820m	9.219ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.925m	10.370ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	19.072m	9.901ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	32.965m	12.323ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.332m	2.277ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.819m	2.683ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.554m	3.048ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.621m	2.129ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.190m	5.874ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.706m	3.255ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.728m	4.966ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.396m	2.878ms	1	1	100.00
		chip_tap_straps_rma	4.767m	6.449ms	1	1	100.00
		chip_tap_straps_prod	8.005m	8.345ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.582m	3.304ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.114m	7.482ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.554m	4.608ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.629m	43.047ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.868m	3.060ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.474m	6.402ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.388m	6.782ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.609m	6.690ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.055m	8.761ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.338m	7.299ms	1	1	100.00
		chip_prim_tl_access	3.216m	7.868ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.925m	10.832ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.210m	3.216ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.924m	4.272ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.486m	3.650ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.586m	4.713ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.912m	3.885ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.975m	4.678ms	1	1	100.00
		chip_tap_straps_dev	1.396m	2.878ms	1	1	100.00
		chip_tap_straps_rma	4.767m	6.449ms	1	1	100.00
		chip_tap_straps_prod	8.005m	8.345ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.296m	14.766ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.561m	4.216ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.747m	2.964ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.703m	3.436ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.854m	2.665ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.552m	22.326ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.296m	14.766ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	57.987m	50.414ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.088h	50.192ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.787m	9.002ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.090h	45.987ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	19.552m	22.326ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.151m	1.897ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.214m	2.306ms	1	1	100.00
		rom_volatile_raw_unlock	1.295m	2.205ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.371m	16.538ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.747m	18.473ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.523m	5.865ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.523m	5.865ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.523m	5.865ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.448m	4.157ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.979m	19.894ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.448m	4.157ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.030m	3.930ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.065m	3.004ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.979m	19.894ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.448m	4.157ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.561m	8.041ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.030m	3.930ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.065m	3.004ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.221m	4.063ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.582m	3.304ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.868m	3.060ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.474m	6.402ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.388m	6.782ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.609m	6.690ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.051m	12.904ms	1	1	100.00
		chip_prim_tl_access	3.216m	7.868ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.216m	7.868ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.430m	9.234ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.627m	7.691ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.953m	28.006ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.349m	7.781ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.178m	8.254ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.121m	6.677ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.947m	23.479ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.861m	16.698ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	5.664m	6.678ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.823m	11.738ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.525m	4.955ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.627m	7.691ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.018m	4.264ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	35.814m	35.962ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.150m	5.826ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.058m	5.575ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	15.130m	14.272ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.295m	2.738ms	0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	15.886m	9.246ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.983m	24.513ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.212m	2.798ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.055m	8.761ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.055m	8.761ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.886m	9.246ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	15.130m	14.272ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	5.525m	4.955ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.365m	5.527ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.293m	4.644ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.720m	5.166ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.098m	3.896ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.099m	9.181ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.211m	2.306ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.179m	6.824ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.790m	4.352ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.466m	5.064ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.077m	2.902ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.065m	3.004ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.720m	5.166ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.720m	5.166ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	5.351m	6.452ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.359m	13.690ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.293m	4.644ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.019m	5.096ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.960m	5.568ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.767m	6.449ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.296m	14.766ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.567m	5.303ms	1	1	100.00
		chip_plic_all_irqs_10	3.595m	3.667ms	1	1	100.00
		chip_plic_all_irqs_20	5.057m	4.167ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.543m	3.070ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.203m	2.932ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.675m	15.009ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.156m	7.035ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.828m	2.791ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.554m	3.113ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.591m	3.138ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.030m	3.930ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.531m	4.789ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.420m	6.767ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.254m	8.452ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.338m	7.299ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.744m	5.222ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.295m	2.738ms	0	1	0.00
		chip_sw_sysrst_ctrl_reset	17.444m	23.793ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.834m	3.245ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.691m	3.449ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.498m	4.279ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.444m	23.793ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.444m	23.793ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.048m	2.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.048m	2.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.736m	5.502ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.148m	34.601ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.335m	2.881ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.013m	2.692ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.583m	3.737ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.694m	4.629ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.623m	8.398ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.325h	31.763ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.520m	11.639ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.938m	2.192ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.621m	3.112ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.707m	2.579ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.484h	71.235ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.264m	3.245ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.862m	10.910ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.025m	10.632ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.422m	11.582ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.233m	5.005ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.198m	3.451ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.999m	3.683ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.935s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.528m	5.306ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.247m	2.896ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.866m	4.430ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.900m	9.760ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.709m	2.630ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.354m	4.890ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.147m	2.319ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.783m	5.191ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.002m	5.332ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.526m	4.721ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.886m	9.246ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.862m	10.910ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.025m	10.632ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.422m	11.582ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.157m	3.920ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.691m	6.417ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.412h	38.251ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.412h	38.251ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.274m	2.744ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.761m	3.620ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	45.695m	19.012ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.513m	2.858ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.506m	5.409ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.843m	2.470ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.485m	3.277ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.913m	3.225ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.946s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.493m	3.002ms	1	1	100.00
		TOTAL			282	325	86.77

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.47607348011249393705005664832493704619741714112582203160159952251612252212702
    Line 600, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.40915000754210048696306081937438368861001230785683299290550562700695177222419
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.103973869484541911454310645681335966705918216783339576002980294394792870442877
    Line 733, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.20104462531692618556755888579763653716208002027852571114944102167463510355807
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.97483845737033016076701304129255202552116695008105056100057472551588775624096
    Line 746, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.109750362998790714174504541547639742760568661511311630800998730041224404744885
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.102771423205354914491060386310504369117444970582125957789047005083290976646744
    Line 605, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.32761321543436588315989909870393551395534959500467976478001235173324032733691
    Line 595, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.91302292663563175226099000526236236446111254021872327318751684337343237601997
    Line 600, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.54174794820419408336319025412089127635078834094898162057369842159636139159401
    Line 598, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.43268228894450946900862105883370828594398291711697520810958679564842581208296
    Line 711, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.20677361867079253921512097515034849501517218529217654095544459450653991878894
    Line 727, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.9466541168694845914744256276991090311562524905956783195289004212237272421873
    Line 632, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.99377420699674772197664030808345650099052944851150289006421951436726865168854
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.152s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.25666734578139814718577075649404400541729689252906327527239472446296470008985
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.146s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.19684800401400708389036171277353045861179172301527866807967625721366567487224
    Line 818, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.68761041632074691241639556962215164215428196271351352839123461231693060523140
    Line 750, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.20771840150316079796292698670432607652345122574855003816735588264560781668591
    Line 736, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.111768881046875333227660670953048404144233619440196830576939653839768028821428
    Line 805, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12981531918861166419374546887883218568166721888092883258929941499521840398222
    Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2791.406410 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2791.406410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86677) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.110286682332688863997406806527061985169734928979775452275251789160881753171663
Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5166.271374 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86677) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5166.271374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sysrst_ctrl_reset.109333781375816163727355318707687017033284609382229863800517990108607455135898
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log
```
  UVM_ERROR @ 2737.532970 us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2737.532970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.97307298238040947562255196763307650655676390273881295250648342077496290050889
    Line 507, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 14271.792652 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 14271.792652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.58322011568042526810439159336446954882015725639828101705455740531823967924839
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 2578.710200 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2578.710200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.55412094095272112419057772779867239274515741886723066869978028395888017704434
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34600.902235 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34600.902235 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.39533527533658177453457979341419500353935582940547878942437757899689322678625
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2441.786052 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2441.786052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.27547641162479956934540784814661244441326704589377381071749139238495543517070
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3009.706696 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3009.706696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.43300066223269661617733335490263379533143111057285147740351894409292641163340
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2917.179905 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2917.179905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44383) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.37321384400220796552928628940884831368958188625413294004499852413071928119414
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2964.096108 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44383) { a_addr: 'h1051c  a_data: 'hd4a00f3f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1ae15  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2964.096108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.10011118405846138060907538031705790649834622184451925690362298811098203224391
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3225.339460 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3225.339460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.69753552773737696759254005646790535987077469111669988419280208323305998869955
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3586.082500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3586.082500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.97176809422679297992087399166968761333791650412755654785812733953508651826776
    Line 426, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2433.300000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2433.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.49873972954947489130821647125988834921429337652534110670096850303392769136488
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 12803.116053 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 12803.116053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.87344147230209881870124331726485276792071594191331550183936137684528824709221
    Line 473, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3245.190025 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3245.190025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.26703534681699167593792229465717616208498274214843389282747080990418002482157
    Line 675, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.10674630067404512770871798362936367842594515320959245050738904742115202388805
    Line 626, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.85468516452777056403843868126831177743084538126478652956065236769294440477081
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2692.150852 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h10300  a_data: 'h984a376d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h4  a_user: 'h18aaa  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2692.150852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---