ADC_CTRL Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.250s	5.813ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.960s	851.137us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.980s	561.063us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	10.350s	22.955ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.480s	936.217us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.890s	542.323us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.980s	561.063us	1	1	100.00
		adc_ctrl_csr_aliasing	2.480s	936.217us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.841m	161.716ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.234m	170.489ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.252m	169.358ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.930m	320.039ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.661m	569.058ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.342m	587.792ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.226m	535.375ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.375m	204.956ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.570s	3.066ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	20.100s	20.592ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.346m	89.150ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	7.130s	5.069ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.950s	432.728us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.540s	419.722us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.840s	383.964us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.840s	383.964us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.960s	851.137us	1	1	100.00
		adc_ctrl_csr_rw	1.980s	561.063us	1	1	100.00
		adc_ctrl_csr_aliasing	2.480s	936.217us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.930s	2.166ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.960s	851.137us	1	1	100.00
		adc_ctrl_csr_rw	1.980s	561.063us	1	1	100.00
		adc_ctrl_csr_aliasing	2.480s	936.217us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.930s	2.166ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	6.380s	3.843ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.950s	9.425ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.950s	9.425ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.070s	6.272ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00