AES/MASKED Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	107.824us	1	1	100.00
V1	smoke	aes_smoke	5.000s	98.595us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	69.389us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	87.851us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	243.159us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	91.500us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	57.469us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	87.851us	1	1	100.00
		aes_csr_aliasing	4.000s	91.500us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	98.595us	1	1	100.00
		aes_config_error	5.000s	99.813us	1	1	100.00
		aes_stress	5.000s	89.187us	1	1	100.00
V2	key_length	aes_smoke	5.000s	98.595us	1	1	100.00
		aes_config_error	5.000s	99.813us	1	1	100.00
		aes_stress	5.000s	89.187us	1	1	100.00
V2	back2back	aes_stress	5.000s	89.187us	1	1	100.00
		aes_b2b	5.000s	63.480us	1	1	100.00
V2	backpressure	aes_stress	5.000s	89.187us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	98.595us	1	1	100.00
		aes_config_error	5.000s	99.813us	1	1	100.00
		aes_stress	5.000s	89.187us	1	1	100.00
		aes_alert_reset	6.000s	205.647us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	99.047us	1	1	100.00
		aes_config_error	5.000s	99.813us	1	1	100.00
		aes_alert_reset	6.000s	205.647us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	269.845us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	174.577us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	205.647us	1	1	100.00
V2	stress	aes_stress	5.000s	89.187us	1	1	100.00
V2	sideload	aes_stress	5.000s	89.187us	1	1	100.00
		aes_sideload	5.000s	81.674us	1	1	100.00
V2	deinitialization	aes_deinit	4.000s	62.836us	1	1	100.00
V2	stress_all	aes_stress_all	10.000s	191.867us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	82.174us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	81.334us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	81.334us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	69.389us	1	1	100.00
		aes_csr_rw	5.000s	87.851us	1	1	100.00
		aes_csr_aliasing	4.000s	91.500us	1	1	100.00
		aes_same_csr_outstanding	4.000s	100.044us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	69.389us	1	1	100.00
		aes_csr_rw	5.000s	87.851us	1	1	100.00
		aes_csr_aliasing	4.000s	91.500us	1	1	100.00
		aes_same_csr_outstanding	4.000s	100.044us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	174.826us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	149.293us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	823.609us	1	1	100.00
		aes_tl_intg_err	4.000s	116.263us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	116.263us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	205.647us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	98.595us	1	1	100.00
		aes_stress	5.000s	89.187us	1	1	100.00
		aes_alert_reset	6.000s	205.647us	1	1	100.00
		aes_core_fi	5.000s	132.246us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	74.428us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	52.664us	1	1	100.00
		aes_stress	5.000s	89.187us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	89.187us	1	1	100.00
		aes_sideload	5.000s	81.674us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	52.664us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	52.664us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	52.664us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	52.664us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	52.664us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	89.187us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	89.187us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	184.159us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	184.159us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	61.137us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	184.159us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	205.647us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_ctr_fi	4.000s	53.304us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	184.159us	1	1	100.00
		aes_control_fi	17.000s	10.011ms	0	1	0.00
		aes_cipher_fi	4.000s	61.137us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	24.000s	4.987ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.45125486235936623919790718555957218154185923549480614209124253976755672394474
      Line 130, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        UVM_FATAL @ 10011335627 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10011335627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.22195187588130660462226278175558757682866457574303724668283090472492579899276
      Line 297, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4986711254 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4986711254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---