| V1 |
smoke |
aon_timer_smoke |
1.680s |
704.222us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.780s |
942.291us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
2.200s |
500.838us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
4.650s |
6.701ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
2.310s |
625.320us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.910s |
482.320us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
2.200s |
500.838us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.310s |
625.320us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
1.810s |
460.143us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
1.810s |
334.405us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
1.810s |
722.562us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
1.880s |
579.063us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
27.950s |
89.095ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
1.960s |
499.523us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
1.620s |
331.518us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
2.810s |
552.994us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
2.810s |
552.994us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.780s |
942.291us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
2.200s |
500.838us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.310s |
625.320us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.870s |
1.632ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.780s |
942.291us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
2.200s |
500.838us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.310s |
625.320us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.870s |
1.632ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
10.310s |
7.989ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
4.000s |
4.432ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
4.000s |
4.432ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
1.830s |
490.307us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.930s |
544.486us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
4.200s |
3.476ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
2.290s |
684.901us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
4.500s |
4.142ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
20.080s |
4.486ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |