EDN Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.210s 24.314us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.060s 21.780us 1 1 100.00
V1 csr_rw edn_csr_rw 2.420s 18.138us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.590s 58.572us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.880s 16.218us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.420s 36.552us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.420s 18.138us 1 1 100.00
edn_csr_aliasing 1.880s 16.218us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.000s 26.851us 1 1 100.00
V2 csrng_commands edn_genbits 2.000s 26.851us 1 1 100.00
V2 genbits edn_genbits 2.000s 26.851us 1 1 100.00
V2 interrupts edn_intr 1.850s 25.700us 1 1 100.00
V2 alerts edn_alert 1.960s 124.056us 1 1 100.00
V2 errs edn_err 1.690s 30.468us 1 1 100.00
V2 disable edn_disable 1.630s 11.666us 1 1 100.00
edn_disable_auto_req_mode 1.840s 118.175us 1 1 100.00
V2 stress_all edn_stress_all 3.820s 318.454us 1 1 100.00
V2 intr_test edn_intr_test 1.630s 23.947us 1 1 100.00
V2 alert_test edn_alert_test 1.840s 53.922us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.800s 67.989us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.800s 67.989us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.060s 21.780us 1 1 100.00
edn_csr_rw 2.420s 18.138us 1 1 100.00
edn_csr_aliasing 1.880s 16.218us 1 1 100.00
edn_same_csr_outstanding 2.610s 77.104us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.060s 21.780us 1 1 100.00
edn_csr_rw 2.420s 18.138us 1 1 100.00
edn_csr_aliasing 1.880s 16.218us 1 1 100.00
edn_same_csr_outstanding 2.610s 77.104us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.140s 466.893us 1 1 100.00
edn_tl_intg_err 3.680s 130.720us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.860s 17.474us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.960s 124.056us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.140s 466.893us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.140s 466.893us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.140s 466.893us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.140s 466.893us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.960s 124.056us 1 1 100.00
edn_sec_cm 7.140s 466.893us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.960s 124.056us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.680s 130.720us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets