| V1 |
smoke |
hmac_smoke |
3.930s |
350.403us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.620s |
30.826us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.870s |
32.423us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
10.560s |
1.174ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
6.630s |
162.525us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
2.310s |
89.323us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.870s |
32.423us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.630s |
162.525us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
52.150s |
8.647ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
55.460s |
6.343ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
8.780s |
186.824us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.426m |
38.898ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.680s |
2.854ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.530s |
250.517us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.340s |
882.993us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.600s |
236.996us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
6.230s |
3.788ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
8.743m |
3.635ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
38.310s |
3.190ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
43.600s |
1.287ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
3.930s |
350.403us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
52.150s |
8.647ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
55.460s |
6.343ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
8.743m |
3.635ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
6.230s |
3.788ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
3.806m |
3.920ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
3.930s |
350.403us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
52.150s |
8.647ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
55.460s |
6.343ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
8.743m |
3.635ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
43.600s |
1.287ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.780s |
186.824us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.426m |
38.898ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.680s |
2.854ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.530s |
250.517us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.340s |
882.993us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.600s |
236.996us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
3.930s |
350.403us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
52.150s |
8.647ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
55.460s |
6.343ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
8.743m |
3.635ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
6.230s |
3.788ms |
1 |
1 |
100.00 |
|
|
hmac_error |
38.310s |
3.190ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
43.600s |
1.287ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.780s |
186.824us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.426m |
38.898ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.680s |
2.854ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.530s |
250.517us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.340s |
882.993us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.600s |
236.996us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
3.806m |
3.920ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
3.806m |
3.920ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.440s |
15.668us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.430s |
74.100us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
3.170s |
270.975us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
3.170s |
270.975us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.620s |
30.826us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.870s |
32.423us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.630s |
162.525us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.770s |
257.923us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.620s |
30.826us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.870s |
32.423us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.630s |
162.525us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.770s |
257.923us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.610s |
199.438us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
2.370s |
318.349us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
2.370s |
318.349us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
3.930s |
350.403us |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
1.980s |
22.726us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
41.810s |
3.603ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
1.750s |
23.712us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |