I2C Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.820s	3.798ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	6.670s	2.146ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	41.239us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.520s	77.159us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.070s	657.399us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.300s	44.053us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.100s	97.616us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.520s	77.159us	1	1	100.00
		i2c_csr_aliasing	2.300s	44.053us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.160s	606.474us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.688m	14.147ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	46.530s	3.042ms	1	1	100.00
V2	host_override	i2c_host_override	1.440s	15.032us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.522m	20.395ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.352m	3.917ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.100s	143.884us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.450s	2.037ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.730s	113.396us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.849m	10.175ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.640s	4.724ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.900s	86.605us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.310s	9.415ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.481m	54.235ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.350s	3.242ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.790s	426.397us	1	1	100.00
		i2c_target_intr_smoke	4.250s	837.361us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.090s	134.354us	1	1	100.00
		i2c_target_fifo_reset_tx	2.300s	1.236ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.077m	38.427ms	1	1	100.00
		i2c_target_stress_rd	12.790s	426.397us	1	1	100.00
		i2c_target_intr_stress_wr	8.310s	4.545ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.130s	1.029ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	51.510s	3.968ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.140s	3.655ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.630s	10.004ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.550s	454.135us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.990s	637.571us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	46.530s	3.042ms	1	1	100.00
		i2c_host_perf_precise	6.040s	1.626ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.640s	4.724ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.570s	86.585us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.850s	2.260ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.530s	1.883ms	1	1	100.00
		i2c_target_nack_txstretch	2.410s	550.916us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.330s	221.253us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.910s	1.347ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.570s	22.500us	1	1	100.00
V2	intr_test	i2c_intr_test	1.600s	37.788us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.350s	137.005us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.350s	137.005us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	41.239us	1	1	100.00
		i2c_csr_rw	1.520s	77.159us	1	1	100.00
		i2c_csr_aliasing	2.300s	44.053us	1	1	100.00
		i2c_same_csr_outstanding	1.740s	142.108us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	41.239us	1	1	100.00
		i2c_csr_rw	1.520s	77.159us	1	1	100.00
		i2c_csr_aliasing	2.300s	44.053us	1	1	100.00
		i2c_same_csr_outstanding	1.740s	142.108us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.030s	57.767us	1	1	100.00
		i2c_sec_cm	1.680s	185.866us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.030s	57.767us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.880s	2.597ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.130s	143.567us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	16.500s	8.604ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.45345819376416184043558696801516337234126546074660104422147820384758144272634
      Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2596579146 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2596579146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.56175499317655777433394299878248755990545862507400445344833655941001328844145
      Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8604377631 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8604377631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.80646524384609352248308193790494306311037417614285572705322879567879715416524
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 143566616 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 143566616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.10524902137453463172985038278231683414176817334555152007732769677917046850086
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10004144246 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10004144246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[NOA] Null object access has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.106863696350059351975713137416605825572584751347297436689359397953263071195994
      Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        Error-[NOA] Null object access
        ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.62995597747619975434195642022437393339086331304818436808991669912035726389984
      Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.