KMAC/MASKED Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.590s	224.088us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.940s	29.586us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.840s	22.860us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.480s	1.170ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.060s	988.544us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.290s	115.013us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	22.860us	1	1	100.00
		kmac_csr_aliasing	4.060s	988.544us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.650s	13.792us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.930s	33.405us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.563m	176.234ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.472m	34.309ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.209m	19.680ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.455m	312.101ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.580s	4.586ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.888m	83.178ms	1	1	100.00
		kmac_test_vectors_shake_128	35.074m	292.853ms	1	1	100.00
		kmac_test_vectors_shake_256	1.416m	2.741ms	1	1	100.00
		kmac_test_vectors_kmac	3.270s	42.550us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.570s	68.935us	1	1	100.00
V2	sideload	kmac_sideload	5.820s	869.071us	1	1	100.00
V2	app	kmac_app	4.320m	28.809ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.908m	61.045ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.474m	21.005ms	1	1	100.00
V2	error	kmac_error	52.490s	4.141ms	1	1	100.00
V2	key_error	kmac_key_error	8.430s	1.981ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.780s	61.131us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.110s	605.487us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.640s	27.331us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.330s	327.624us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.220s	96.413us	1	1	100.00
V2	stress_all	kmac_stress_all	7.463m	20.365ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.670s	16.003us	1	1	100.00
V2	alert_test	kmac_alert_test	1.770s	27.324us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.200s	25.818us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.200s	25.818us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.940s	29.586us	1	1	100.00
		kmac_csr_rw	1.840s	22.860us	1	1	100.00
		kmac_csr_aliasing	4.060s	988.544us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	54.433us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.940s	29.586us	1	1	100.00
		kmac_csr_rw	1.840s	22.860us	1	1	100.00
		kmac_csr_aliasing	4.060s	988.544us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	54.433us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.110s	96.377us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.110s	96.377us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.110s	96.377us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.110s	96.377us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.630s	195.845us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.176m	7.942ms	1	1	100.00
		kmac_tl_intg_err	1.850s	102.560us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.850s	102.560us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.220s	96.413us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.590s	224.088us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.820s	869.071us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.110s	96.377us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.176m	7.942ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.176m	7.942ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.176m	7.942ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.590s	224.088us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.220s	96.413us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.176m	7.942ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.775m	63.470ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.590s	224.088us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.350s	185.833us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.107655487202104093166389179299537243044576329067677647073000765467158914596713
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 185833089 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 185833089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.74437491446574432392389078340096710423044559567791490218528765878002398896268
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @ 102560204 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @ 102560204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---