PATTGEN Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	38.448us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	16.997us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	50.040us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	726.869us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	18.825us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	20.910us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	50.040us	1	1	100.00
		pattgen_csr_aliasing	4.000s	18.825us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	28.000s	10.974ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	4.000s	98.317us	1	1	100.00
V2	error	pattgen_error	4.000s	40.674us	1	1	100.00
V2	stress_all	pattgen_stress_all	6.000s	82.572us	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	49.614us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	14.367us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	59.032us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	59.032us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	16.997us	1	1	100.00
		pattgen_csr_rw	4.000s	50.040us	1	1	100.00
		pattgen_csr_aliasing	4.000s	18.825us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	75.964us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	16.997us	1	1	100.00
		pattgen_csr_rw	4.000s	50.040us	1	1	100.00
		pattgen_csr_aliasing	4.000s	18.825us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	75.964us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	51.835us	1	1	100.00
		pattgen_sec_cm	4.000s	157.729us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	51.835us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.000s	34.266ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	26.970us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.68180186479195235594016329219066539739706277259736103941384945520568366976542
      Line 123, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4069128597 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 4069138166 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4069138166 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 4069830473 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.110746007366643965746038144920820553210640656225800470568314066008978234129305
      Line 135, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @  82572178 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10271