ROM_CTRL/32KB Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.400s 311.433us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.160s 218.544us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.500s 288.608us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.460s 371.316us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.520s 294.159us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.230s 890.151us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.500s 288.608us 1 1 100.00
rom_ctrl_csr_aliasing 4.520s 294.159us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.220s 170.066us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.940s 173.665us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.490s 139.736us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 21.250s 7.988ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 10.400s 4.163ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.070s 560.652us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.700s 974.904us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.700s 974.904us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.160s 218.544us 1 1 100.00
rom_ctrl_csr_rw 4.500s 288.608us 1 1 100.00
rom_ctrl_csr_aliasing 4.520s 294.159us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.270s 165.434us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.160s 218.544us 1 1 100.00
rom_ctrl_csr_rw 4.500s 288.608us 1 1 100.00
rom_ctrl_csr_aliasing 4.520s 294.159us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.270s 165.434us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.170s 12.517ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
rom_ctrl_tl_intg_err 22.050s 527.567us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.400s 311.433us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.400s 311.433us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.400s 311.433us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 22.050s 527.567us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
rom_ctrl_kmac_err_chk 10.400s 4.163ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 42.420s 2.979ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.170s 12.517ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.090m 1.680ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.438m 3.323ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00